From a3620c264a64b3fc7a9f44330166fdf88cea0136 Mon Sep 17 00:00:00 2001 From: hmeiland Date: Thu, 9 Jul 2026 14:00:16 +0200 Subject: [PATCH 1/6] Add U74 target with a 4x4 register-tiled GEMM kernel The SiFive U74 (RV64GC; e.g. StarFive JH7110 / VisionFive 2) is a scalar, in-order core with no RVV, so today it falls back to RISCV64_GENERIC whose S/D GEMM uses the generic 2x2 C micro-kernel. Per the U74 Core Complex Manual (Table 169) fmadd.d has a 7-cycle latency at repeat rate 1 (fully pipelined). A 2x2 tile exposes only 4 independent accumulator chains -- fewer than the FMA latency -- so the FP pipe stalls on the accumulator dependency, and the 1:1 load:FMA ratio saturates the single load/store pipe ("only one outstanding line fill", manual 8.2). This adds a portable 4x4 GEMM micro-kernel and a dedicated U74 target: - kernel/generic/gemmkernel_4x4.c: 16-accumulator 4x4 register tile. 16 independent chains exceed the 7-cycle latency, and the load:FMA ratio drops to 1:2. 16 acc + 4 A + 4 B fit RV64G's 32 FP registers without spilling. Full 4/2/1 edge handling in both M and N. - U74 target wiring: getarch.c (FORCE_U74, 32 KiB/64 B L1D, 2 MiB L2), param.h (S/D UNROLL 4/4; complex stays 2/2), kernel/riscv64/KERNEL.U74 (S/D GEMM -> gemmkernel_4x4 + gemm_[nt]copy_4; S/D TRMM -> existing trmmkernel_4x4), Makefile.prebuild + Makefile.riscv64 (-mtune=sifive-u74), TargetList.txt, cpuid_riscv64.c. The 4x4 kernel was verified numerically against a naive reference GEMM, driven through the real gemm_tcopy_4 / gemm_ncopy_4 packing routines, across 27,436 M/N/K x alpha combinations covering every 4/2/1 tail case: worst absolute error 0. Build with: make TARGET=U74 --- Makefile.prebuild | 4 + Makefile.riscv64 | 4 + TargetList.txt | 1 + cpuid_riscv64.c | 7 +- getarch.c | 14 ++ kernel/generic/gemmkernel_4x4.c | 264 ++++++++++++++++++++++++++++++++ kernel/riscv64/KERNEL.U74 | 177 +++++++++++++++++++++ param.h | 39 +++++ 8 files changed, 508 insertions(+), 2 deletions(-) create mode 100644 kernel/generic/gemmkernel_4x4.c create mode 100644 kernel/riscv64/KERNEL.U74 diff --git a/Makefile.prebuild b/Makefile.prebuild index b7d695a750..94b47346f6 100644 --- a/Makefile.prebuild +++ b/Makefile.prebuild @@ -75,6 +75,10 @@ ifeq ($(TARGET), RISCV64_GENERIC) TARGET_FLAGS = -march=rv64imafdc -mabi=lp64d endif +ifeq ($(TARGET), U74) +TARGET_FLAGS = -march=rv64imafdc -mabi=lp64d +endif + all: getarch_2nd ./getarch_2nd 0 >> $(TARGET_MAKE) ./getarch_2nd 1 >> $(TARGET_CONF) diff --git a/Makefile.riscv64 b/Makefile.riscv64 index d8da98d5f0..eea7bc4c96 100644 --- a/Makefile.riscv64 +++ b/Makefile.riscv64 @@ -25,3 +25,7 @@ ifeq ($(CORE), RISCV64_GENERIC) CCOMMON_OPT += -march=rv64imafdc -mabi=lp64d FCOMMON_OPT += -march=rv64imafdc -mabi=lp64d endif +ifeq ($(CORE), U74) +CCOMMON_OPT += -march=rv64imafdc -mabi=lp64d -mtune=sifive-u74 +FCOMMON_OPT += -march=rv64imafdc -mabi=lp64d -mtune=sifive-u74 +endif diff --git a/TargetList.txt b/TargetList.txt index e71c697571..377ecc7d0d 100644 --- a/TargetList.txt +++ b/TargetList.txt @@ -128,6 +128,7 @@ RISCV64_ZVL128B C910V x280 RISCV64_ZVL256B +U74 (e.g. SiFive U74 / StarFive JH7110 / VisionFive 2) 11.LOONGARCH64: // LOONGSONGENERIC/LOONGSON2K1000/LOONGSON3R5 are legacy names, diff --git a/cpuid_riscv64.c b/cpuid_riscv64.c index ff7ba2aad4..69adff7180 100644 --- a/cpuid_riscv64.c +++ b/cpuid_riscv64.c @@ -75,13 +75,15 @@ USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define CPU_x280 2 #define CPU_RISCV64_ZVL256B 3 #define CPU_RISCV64_ZVL128B 4 +#define CPU_U74 5 static char *cpuname[] = { "RISCV64_GENERIC", "C910V", "x280", "CPU_RISCV64_ZVL256B", - "CPU_RISCV64_ZVL128B" + "CPU_RISCV64_ZVL128B", + "U74" }; static char *cpuname_lower[] = { @@ -89,7 +91,8 @@ static char *cpuname_lower[] = { "c910v", "x280", "riscv64_zvl256b", - "riscv64_zvl128b" + "riscv64_zvl128b", + "u74" }; int detect(void){ diff --git a/getarch.c b/getarch.c index d2dd8c6c48..ea0c52c368 100644 --- a/getarch.c +++ b/getarch.c @@ -1232,6 +1232,20 @@ USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #else #endif +#ifdef FORCE_U74 +#define FORCE +#define ARCHITECTURE "RISCV64" +#define SUBARCHITECTURE "U74" +#define SUBDIRNAME "riscv64" +#define ARCHCONFIG "-DU74 " \ + "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \ + "-DL2_SIZE=2097152 -DL2_LINESIZE=64 " \ + "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 " +#define LIBNAME "u74" +#define CORENAME "U74" +#else +#endif + #ifdef FORCE_WASM128_GENERIC #define FORCE #define ARCHITECTURE "WASM" diff --git a/kernel/generic/gemmkernel_4x4.c b/kernel/generic/gemmkernel_4x4.c new file mode 100644 index 0000000000..b78eb76ea2 --- /dev/null +++ b/kernel/generic/gemmkernel_4x4.c @@ -0,0 +1,264 @@ +/*************************************************************************** + * Copyright (c) 2026, The OpenBLAS Project + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of the OpenBLAS project nor the names of + * its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * *****************************************************************************/ + +/* + * Portable C GEMM micro-kernel with a 4x4 register tile (16 accumulators). + * + * This is a wider companion to gemmkernel_2x2.c intended for in-order scalar + * cores whose FP FMA has a multi-cycle latency but 1/cycle throughput (e.g. + * SiFive U74: fmadd.d latency 7, repeat rate 1). A 2x2 tile exposes only 4 + * independent accumulator chains, which is fewer than the FMA latency and + * leaves the FP pipe stalled on the accumulator dependency. A 4x4 tile keeps + * 16 independent chains -- comfortably above the latency -- and lowers the + * load:FMA ratio from 1:1 to 1:2, so the single load/store pipe stops being + * the bottleneck. RV64G has 32 FP registers, so 16 accumulators + 4 A + 4 B + * fit without spilling. + * + * Packed-data contract (identical to the 2x2 kernel, verified against the + * generic tcopy_4 / ncopy_4 copy routines): the A operand is packed by + * tcopy_ into MR-row micro-panels [A(r0,k)..A(r3,k)] per k, and the + * B operand by ncopy_ into NR-col micro-panels [B(k,c0)..B(k,c3)] + * per k. Both dimensions are decomposed as 4 / 2 / 1 sub-blocks at the edges. + */ + +#include "common.h" + +#include "conversion_macros.h" + +#ifdef BGEMM +#define C_TO_F32 TO_F32 +#else +#define C_TO_F32 +#endif + +int CNAME(BLASLONG bm,BLASLONG bn,BLASLONG bk,FLOAT alpha,IFLOAT* ba,IFLOAT* bb,FLOAT* C,BLASLONG ldc +#ifdef TRMMKERNEL + ,BLASLONG offset +#endif + ) +{ + BLASLONG i,j,k; + FLOAT *C0,*C1,*C2,*C3; + IFLOAT *ptrba,*ptrbb; + FLOAT r0c0,r1c0,r2c0,r3c0; + FLOAT r0c1,r1c1,r2c1,r3c1; + FLOAT r0c2,r1c2,r2c2,r3c2; + FLOAT r0c3,r1c3,r2c3,r3c3; + IFLOAT a0,a1,a2,a3,b0,b1,b2,b3; + + /* ==================== N panels of 4 ==================== */ + for (j=0; j Date: Thu, 9 Jul 2026 20:21:40 +0200 Subject: [PATCH 2/6] U74 target: build for the full JH7110 ISA (add Zba/Zbb) The StarFive JH7110's U74 cores implement rv64imafdc_..._zba_zbb, so the U74 target now compiles with -march=rv64imafdc_zba_zbb. The generic RISCV64_GENERIC target stays at bare rv64imafdc for portability across unknown RV64GC cores. Measured on the VisionFive 2 (GCC 13.3, -mtune=sifive-u74 held constant): GCC emits Zba shift-add instructions in the packing routines, but DGEMM is unchanged -- the 4x4 kernel holds 1.533 GF either way and packing 1.74 vs 1.75 GB/s. The 4x4 micro-kernel is FMA-bound (fused fmadd.d with immediate-offset loads) and packing is LPDDR4-bandwidth-bound, so integer address generation is not on the critical path. The flag is nonetheless the correct -march for the silicon, is free, and can only help address-gen-bound code elsewhere in the library. The remaining GEMM headroom on the U74 is microarchitectural scheduling (a hand-written assembly micro-kernel), not the ISA. --- Makefile.prebuild | 2 +- Makefile.riscv64 | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Makefile.prebuild b/Makefile.prebuild index 94b47346f6..6b2567cb90 100644 --- a/Makefile.prebuild +++ b/Makefile.prebuild @@ -76,7 +76,7 @@ TARGET_FLAGS = -march=rv64imafdc -mabi=lp64d endif ifeq ($(TARGET), U74) -TARGET_FLAGS = -march=rv64imafdc -mabi=lp64d +TARGET_FLAGS = -march=rv64imafdc_zba_zbb -mabi=lp64d endif all: getarch_2nd diff --git a/Makefile.riscv64 b/Makefile.riscv64 index eea7bc4c96..7ee92a46f0 100644 --- a/Makefile.riscv64 +++ b/Makefile.riscv64 @@ -26,6 +26,6 @@ CCOMMON_OPT += -march=rv64imafdc -mabi=lp64d FCOMMON_OPT += -march=rv64imafdc -mabi=lp64d endif ifeq ($(CORE), U74) -CCOMMON_OPT += -march=rv64imafdc -mabi=lp64d -mtune=sifive-u74 -FCOMMON_OPT += -march=rv64imafdc -mabi=lp64d -mtune=sifive-u74 +CCOMMON_OPT += -march=rv64imafdc_zba_zbb -mabi=lp64d -mtune=sifive-u74 +FCOMMON_OPT += -march=rv64imafdc_zba_zbb -mabi=lp64d -mtune=sifive-u74 endif From e4228c32556b205d6b6ae0fbfdde321ed0e248ec Mon Sep 17 00:00:00 2001 From: hmeiland Date: Fri, 10 Jul 2026 01:26:18 +0200 Subject: [PATCH 3/6] U74 target: raise DGEMM_DEFAULT_Q to 256 A same-board controlled HPL A/B (VisionFive 2, TARGET=U74, N=10000, NB=192, 2x2 grid, both libraries clean-built, residual PASSED) measures 4.97 vs 4.86 GFLOPS (+2.25%) for DGEMM_Q=256 over the inherited 128; at a memory-filling N=27456 the tuned build sustains 5.41 vs 5.24 GFLOPS (+3.24%). With HPL's NB=192, KC=256>=192 lets each trailing-update K panel run in a single KC block, halving the C read-modify-write traffic versus KC=128 (which splits K=192 into 128+64). A single-core P/Q sweep over the real packing + micro-kernel objects confirms the GEMM is compute-bound (whole grid within 3%), so P and R are left unchanged; SGEMM_Q was already 240. --- param.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/param.h b/param.h index 7edfe7e187..c1b858cdfa 100644 --- a/param.h +++ b/param.h @@ -3113,7 +3113,7 @@ USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define ZGEMM_DEFAULT_P 64 #define SGEMM_DEFAULT_Q 240 -#define DGEMM_DEFAULT_Q 128 +#define DGEMM_DEFAULT_Q 256 #define CGEMM_DEFAULT_Q 120 #define ZGEMM_DEFAULT_Q 120 From 4999e881a5503f9bf3bff7fd5947d8b452d99992 Mon Sep 17 00:00:00 2001 From: hmeiland Date: Fri, 10 Jul 2026 03:31:45 +0200 Subject: [PATCH 4/6] U74 target: hand-scheduled scalar asm DGEMM micro-kernel Adds a hand-written RV64GC scalar 4x4 DGEMM micro-kernel (kern_u74.S) and wires it as the U74 DGEMMKERNEL via a hybrid dispatcher (gemmkernel_4x4_u74.c): the fast path (bm,bn multiples of 4, even bk, non-TRMM) runs the asm; all other shapes, odd bk, and the TRMM builds fall back to the portable C 4x4 kernel. The asm uses a 4x4 register tile (16 accumulators), full operand double- buffering (P/Q ping-pong) with one-iteration lookahead, and load-before-FMA issue ordering matched to the U74's dual-issue in-order front end. Probes show this reaches the FP-pipe peak (~16.5 cycles / 16 fmadd.d = 2.9 GF on L1-resident data); the streaming plateau is memory-latency-bound, not the schedule. Measured on a VisionFive 2 (single-core, KC=256): micro-kernel 1.88 vs 1.54 GF (+22%), full blocked DGEMM 1.77 vs 1.48 GF (+20%); the advantage holds under 4-core contention (+17%). End-to-end HPL N=10000 (4 cores, Q=256): 5.17 vs 4.97 GF (+4.0%), residual PASSED. Correctness validated against the full BLAS Level-3 test suite (DGEMM 17,496 computational calls, 0 failures). kern_u74.S is the readable source; the .c embeds it via top-level __asm__ so it builds as a single OpenBLAS kernel object with no build-system changes. --- kernel/generic/gemmkernel_4x4_u74.c | 525 ++++++++++++++++++++++++++++ kernel/generic/kern_u74.S | 267 ++++++++++++++ kernel/riscv64/KERNEL.U74 | 2 +- 3 files changed, 793 insertions(+), 1 deletion(-) create mode 100644 kernel/generic/gemmkernel_4x4_u74.c create mode 100644 kernel/generic/kern_u74.S diff --git a/kernel/generic/gemmkernel_4x4_u74.c b/kernel/generic/gemmkernel_4x4_u74.c new file mode 100644 index 0000000000..42fe108ce0 --- /dev/null +++ b/kernel/generic/gemmkernel_4x4_u74.c @@ -0,0 +1,525 @@ +/*************************************************************************** + * Copyright (c) 2026, The OpenBLAS Project + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of the OpenBLAS project nor the names of + * its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * *****************************************************************************/ + +/* + * Portable C GEMM micro-kernel with a 4x4 register tile (16 accumulators). + * + * This is a wider companion to gemmkernel_2x2.c intended for in-order scalar + * cores whose FP FMA has a multi-cycle latency but 1/cycle throughput (e.g. + * SiFive U74: fmadd.d latency 7, repeat rate 1). A 2x2 tile exposes only 4 + * independent accumulator chains, which is fewer than the FMA latency and + * leaves the FP pipe stalled on the accumulator dependency. A 4x4 tile keeps + * 16 independent chains -- comfortably above the latency -- and lowers the + * load:FMA ratio from 1:1 to 1:2, so the single load/store pipe stops being + * the bottleneck. RV64G has 32 FP registers, so 16 accumulators + 4 A + 4 B + * fit without spilling. + * + * Packed-data contract (identical to the 2x2 kernel, verified against the + * generic tcopy_4 / ncopy_4 copy routines): the A operand is packed by + * tcopy_ into MR-row micro-panels [A(r0,k)..A(r3,k)] per k, and the + * B operand by ncopy_ into NR-col micro-panels [B(k,c0)..B(k,c3)] + * per k. Both dimensions are decomposed as 4 / 2 / 1 sub-blocks at the edges. + */ + +/* + * U74 hybrid variant. The DGEMM fast path (bm, bn multiples of 4, even bk, + * non-TRMM) is served by a hand-scheduled scalar assembly micro-kernel, + * dgemm_u74_asm, embedded below via a top-level __asm__ (readable source in + * kern_u74.S in this directory): a 4x4 register tile with full operand + * double-buffering (P/Q ping-pong) and load-before-FMA issue ordering that + * reaches the U74 FP-pipe peak (~16.5 cycles per 16 fmadd.d). All other + * shapes, odd bk, and the TRMM builds fall back to the portable C 4x4 code + * below. Measured ~+20% single-core DGEMM and +4% four-core HPL over the C + * kernel; validated against the full BLAS Level-3 suite (DGEMM 17,496 calls, + * 0 failures) and HPL (residual PASSED). + */ + +#include "common.h" + +#include "conversion_macros.h" + +#ifdef BGEMM +#define C_TO_F32 TO_F32 +#else +#define C_TO_F32 +#endif + + +extern int dgemm_u74_asm(BLASLONG,BLASLONG,BLASLONG,FLOAT,IFLOAT*,IFLOAT*,FLOAT*,BLASLONG); + +__asm__( + " .text\n" + " .p2align 4\n" + " .type dgemm_u74_asm,@function\n" + "dgemm_u74_asm:\n" + " addi sp, sp, -112\n" + " fsd fs0, 0(sp)\n" + " fsd fs1, 8(sp)\n" + " fsd fs2, 16(sp)\n" + " fsd fs3, 24(sp)\n" + " fsd fs4, 32(sp)\n" + " fsd fs5, 40(sp)\n" + " fsd fs6, 48(sp)\n" + " fsd fs7, 56(sp)\n" + " fsd fs8, 64(sp)\n" + " fsd fs9, 72(sp)\n" + " fsd fs10, 80(sp)\n" + " fsd fs11, 88(sp)\n" + " fsd fa0, 96(sp)\n" + " slli t0, a6, 3\n" + " srli t1, a0, 2\n" + " srli t2, a1, 2\n" + " beqz t2, .Lk4done\n" + ".Lk4j:\n" + " mv a0, a5\n" + " add a1, a0, t0\n" + " add a6, a1, t0\n" + " add a7, a6, t0\n" + " mv t3, a3\n" + " mv t5, t1\n" + ".Lk4i:\n" + " mv t4, a4\n" + " fmv.d.x ft0, zero\n" + " fmv.d.x ft1, zero\n" + " fmv.d.x ft2, zero\n" + " fmv.d.x ft3, zero\n" + " fmv.d.x ft4, zero\n" + " fmv.d.x ft5, zero\n" + " fmv.d.x ft6, zero\n" + " fmv.d.x ft7, zero\n" + " fmv.d.x ft8, zero\n" + " fmv.d.x ft9, zero\n" + " fmv.d.x ft10, zero\n" + " fmv.d.x ft11, zero\n" + " fmv.d.x fa2, zero\n" + " fmv.d.x fa3, zero\n" + " fmv.d.x fa4, zero\n" + " fmv.d.x fa5, zero\n" + " fld fa0, 0(t3)\n" + " fld fa1, 8(t3)\n" + " fld fa6, 16(t3)\n" + " fld fa7, 24(t3)\n" + " fld fs0, 0(t4)\n" + " fld fs1, 8(t4)\n" + " fld fs2, 16(t4)\n" + " fld fs3, 24(t4)\n" + " addi t3, t3, 32\n" + " addi t4, t4, 32\n" + " srli t6, a2, 1\n" + " addi t6, t6, -1\n" + " beqz t6, .Lk4epi\n" + " .p2align 4\n" + ".Lk4body:\n" + " fld fs4, 0(t3)\n" + " fmadd.d ft0, fa0, fs0, ft0\n" + " fld fs5, 8(t3)\n" + " fmadd.d ft1, fa1, fs0, ft1\n" + " fld fs6, 16(t3)\n" + " fmadd.d ft2, fa6, fs0, ft2\n" + " fld fs7, 24(t3)\n" + " fmadd.d ft3, fa7, fs0, ft3\n" + " fld fs8, 0(t4)\n" + " fmadd.d ft4, fa0, fs1, ft4\n" + " fld fs9, 8(t4)\n" + " fmadd.d ft5, fa1, fs1, ft5\n" + " fld fs10, 16(t4)\n" + " fmadd.d ft6, fa6, fs1, ft6\n" + " fld fs11, 24(t4)\n" + " fmadd.d ft7, fa7, fs1, ft7\n" + " addi t3, t3, 32\n" + " fmadd.d ft8, fa0, fs2, ft8\n" + " addi t4, t4, 32\n" + " fmadd.d ft9, fa1, fs2, ft9\n" + " fmadd.d ft10, fa6, fs2, ft10\n" + " fmadd.d ft11, fa7, fs2, ft11\n" + " fmadd.d fa2, fa0, fs3, fa2\n" + " fmadd.d fa3, fa1, fs3, fa3\n" + " fmadd.d fa4, fa6, fs3, fa4\n" + " fmadd.d fa5, fa7, fs3, fa5\n" + " fld fa0, 0(t3)\n" + " fmadd.d ft0, fs4, fs8, ft0\n" + " fld fa1, 8(t3)\n" + " fmadd.d ft1, fs5, fs8, ft1\n" + " fld fa6, 16(t3)\n" + " fmadd.d ft2, fs6, fs8, ft2\n" + " fld fa7, 24(t3)\n" + " fmadd.d ft3, fs7, fs8, ft3\n" + " fld fs0, 0(t4)\n" + " fmadd.d ft4, fs4, fs9, ft4\n" + " fld fs1, 8(t4)\n" + " fmadd.d ft5, fs5, fs9, ft5\n" + " fld fs2, 16(t4)\n" + " fmadd.d ft6, fs6, fs9, ft6\n" + " fld fs3, 24(t4)\n" + " fmadd.d ft7, fs7, fs9, ft7\n" + " addi t3, t3, 32\n" + " fmadd.d ft8, fs4, fs10, ft8\n" + " addi t4, t4, 32\n" + " fmadd.d ft9, fs5, fs10, ft9\n" + " fmadd.d ft10, fs6, fs10, ft10\n" + " fmadd.d ft11, fs7, fs10, ft11\n" + " fmadd.d fa2, fs4, fs11, fa2\n" + " fmadd.d fa3, fs5, fs11, fa3\n" + " fmadd.d fa4, fs6, fs11, fa4\n" + " fmadd.d fa5, fs7, fs11, fa5\n" + " addi t6, t6, -1\n" + " bnez t6, .Lk4body\n" + ".Lk4epi:\n" + " fld fs4, 0(t3)\n" + " fmadd.d ft0, fa0, fs0, ft0\n" + " fld fs5, 8(t3)\n" + " fmadd.d ft1, fa1, fs0, ft1\n" + " fld fs6, 16(t3)\n" + " fmadd.d ft2, fa6, fs0, ft2\n" + " fld fs7, 24(t3)\n" + " fmadd.d ft3, fa7, fs0, ft3\n" + " fld fs8, 0(t4)\n" + " fmadd.d ft4, fa0, fs1, ft4\n" + " fld fs9, 8(t4)\n" + " fmadd.d ft5, fa1, fs1, ft5\n" + " fld fs10, 16(t4)\n" + " fmadd.d ft6, fa6, fs1, ft6\n" + " fld fs11, 24(t4)\n" + " fmadd.d ft7, fa7, fs1, ft7\n" + " addi t3, t3, 32\n" + " fmadd.d ft8, fa0, fs2, ft8\n" + " addi t4, t4, 32\n" + " fmadd.d ft9, fa1, fs2, ft9\n" + " fmadd.d ft10, fa6, fs2, ft10\n" + " fmadd.d ft11, fa7, fs2, ft11\n" + " fmadd.d fa2, fa0, fs3, fa2\n" + " fmadd.d fa3, fa1, fs3, fa3\n" + " fmadd.d fa4, fa6, fs3, fa4\n" + " fmadd.d fa5, fa7, fs3, fa5\n" + " fmadd.d ft0, fs4, fs8, ft0\n" + " fmadd.d ft1, fs5, fs8, ft1\n" + " fmadd.d ft2, fs6, fs8, ft2\n" + " fmadd.d ft3, fs7, fs8, ft3\n" + " fmadd.d ft4, fs4, fs9, ft4\n" + " fmadd.d ft5, fs5, fs9, ft5\n" + " fmadd.d ft6, fs6, fs9, ft6\n" + " fmadd.d ft7, fs7, fs9, ft7\n" + " fmadd.d ft8, fs4, fs10, ft8\n" + " fmadd.d ft9, fs5, fs10, ft9\n" + " fmadd.d ft10, fs6, fs10, ft10\n" + " fmadd.d ft11, fs7, fs10, ft11\n" + " fmadd.d fa2, fs4, fs11, fa2\n" + " fmadd.d fa3, fs5, fs11, fa3\n" + " fmadd.d fa4, fs6, fs11, fa4\n" + " fmadd.d fa5, fs7, fs11, fa5\n" + " fld fs4, 96(sp)\n" + " fld fs0, 0(a0)\n" + " fmadd.d fs0, ft0, fs4, fs0\n" + " fsd fs0, 0(a0)\n" + " fld fs1, 8(a0)\n" + " fmadd.d fs1, ft1, fs4, fs1\n" + " fsd fs1, 8(a0)\n" + " fld fs0, 16(a0)\n" + " fmadd.d fs0, ft2, fs4, fs0\n" + " fsd fs0, 16(a0)\n" + " fld fs1, 24(a0)\n" + " fmadd.d fs1, ft3, fs4, fs1\n" + " fsd fs1, 24(a0)\n" + " fld fs0, 0(a1)\n" + " fmadd.d fs0, ft4, fs4, fs0\n" + " fsd fs0, 0(a1)\n" + " fld fs1, 8(a1)\n" + " fmadd.d fs1, ft5, fs4, fs1\n" + " fsd fs1, 8(a1)\n" + " fld fs0, 16(a1)\n" + " fmadd.d fs0, ft6, fs4, fs0\n" + " fsd fs0, 16(a1)\n" + " fld fs1, 24(a1)\n" + " fmadd.d fs1, ft7, fs4, fs1\n" + " fsd fs1, 24(a1)\n" + " fld fs0, 0(a6)\n" + " fmadd.d fs0, ft8, fs4, fs0\n" + " fsd fs0, 0(a6)\n" + " fld fs1, 8(a6)\n" + " fmadd.d fs1, ft9, fs4, fs1\n" + " fsd fs1, 8(a6)\n" + " fld fs0, 16(a6)\n" + " fmadd.d fs0, ft10, fs4, fs0\n" + " fsd fs0, 16(a6)\n" + " fld fs1, 24(a6)\n" + " fmadd.d fs1, ft11, fs4, fs1\n" + " fsd fs1, 24(a6)\n" + " fld fs0, 0(a7)\n" + " fmadd.d fs0, fa2, fs4, fs0\n" + " fsd fs0, 0(a7)\n" + " fld fs1, 8(a7)\n" + " fmadd.d fs1, fa3, fs4, fs1\n" + " fsd fs1, 8(a7)\n" + " fld fs0, 16(a7)\n" + " fmadd.d fs0, fa4, fs4, fs0\n" + " fsd fs0, 16(a7)\n" + " fld fs1, 24(a7)\n" + " fmadd.d fs1, fa5, fs4, fs1\n" + " fsd fs1, 24(a7)\n" + " addi a0, a0, 32\n" + " addi a1, a1, 32\n" + " addi a6, a6, 32\n" + " addi a7, a7, 32\n" + " addi t5, t5, -1\n" + " bnez t5, .Lk4i\n" + " slli t6, a2, 5\n" + " add a4, a4, t6\n" + " slli t6, t0, 2\n" + " add a5, a5, t6\n" + " addi t2, t2, -1\n" + " bnez t2, .Lk4j\n" + ".Lk4done:\n" + " fld fs0, 0(sp)\n" + " fld fs1, 8(sp)\n" + " fld fs2, 16(sp)\n" + " fld fs3, 24(sp)\n" + " fld fs4, 32(sp)\n" + " fld fs5, 40(sp)\n" + " fld fs6, 48(sp)\n" + " fld fs7, 56(sp)\n" + " fld fs8, 64(sp)\n" + " fld fs9, 72(sp)\n" + " fld fs10, 80(sp)\n" + " fld fs11, 88(sp)\n" + " addi sp, sp, 112\n" + " li a0, 0\n" + " ret\n" + " .size dgemm_u74_asm, .-dgemm_u74_asm\n" +); + +int CNAME(BLASLONG bm,BLASLONG bn,BLASLONG bk,FLOAT alpha,IFLOAT* ba,IFLOAT* bb,FLOAT* C,BLASLONG ldc +#ifdef TRMMKERNEL + ,BLASLONG offset +#endif + ) +{ + BLASLONG i,j,k; + FLOAT *C0,*C1,*C2,*C3; + IFLOAT *ptrba,*ptrbb; + FLOAT r0c0,r1c0,r2c0,r3c0; + FLOAT r0c1,r1c1,r2c1,r3c1; + FLOAT r0c2,r1c2,r2c2,r3c2; + FLOAT r0c3,r1c3,r2c3,r3c3; + IFLOAT a0,a1,a2,a3,b0,b1,b2,b3; + + #if defined(DOUBLE) && !defined(TRMMKERNEL) + if (bm > 0 && bn > 0 && bk > 0 && ((bm & 3) == 0) && ((bn & 3) == 0) && ((bk & 1) == 0)) + return dgemm_u74_asm(bm, bn, bk, alpha, ba, bb, C, ldc); +#endif + + /* ==================== N panels of 4 ==================== */ + for (j=0; j=2); ragged edges + odd bk later. + * + * int kern_asm(long bm,long bn,long bk,double alpha,double* A,double* B,double* C,long ldc) + * a0=bm a1=bn a2=bk fa0=alpha a3=A a4=B a5=C a6=ldc + * acc: col0 ft0..ft3 col1 ft4..ft7 col2 ft8..ft11 col3 fa2..fa5 + * P: A=fa0,fa1,fa6,fa7 B=fs0,fs1,fs2,fs3 Q: A=fs4,fs5,fs6,fs7 B=fs8,fs9,fs10,fs11 + * int: t0=ldc*8 t1=bm/4 t2=j t3=ptrA t4=ptrB t5=i t6=pair-cnt C0..3=a0,a1,a6,a7 + */ + .text + .p2align 4 + .globl kern_asm + .type kern_asm,@function +kern_asm: + addi sp, sp, -112 + fsd fs0, 0(sp) + fsd fs1, 8(sp) + fsd fs2, 16(sp) + fsd fs3, 24(sp) + fsd fs4, 32(sp) + fsd fs5, 40(sp) + fsd fs6, 48(sp) + fsd fs7, 56(sp) + fsd fs8, 64(sp) + fsd fs9, 72(sp) + fsd fs10, 80(sp) + fsd fs11, 88(sp) + fsd fa0, 96(sp) # spill alpha + + slli t0, a6, 3 # ldc*8 + srli t1, a0, 2 # bm/4 + srli t2, a1, 2 # bn/4 (j) + beqz t2, .Ldone + +.Lj: + mv a0, a5 # C0 = Crun + add a1, a0, t0 # C1 + add a6, a1, t0 # C2 + add a7, a6, t0 # C3 + mv t3, a3 # ptrA = ba + mv t5, t1 # i = bm/4 + +.Li: + mv t4, a4 # ptrB = bb(run) + fmv.d.x ft0, zero + fmv.d.x ft1, zero + fmv.d.x ft2, zero + fmv.d.x ft3, zero + fmv.d.x ft4, zero + fmv.d.x ft5, zero + fmv.d.x ft6, zero + fmv.d.x ft7, zero + fmv.d.x ft8, zero + fmv.d.x ft9, zero + fmv.d.x ft10, zero + fmv.d.x ft11, zero + fmv.d.x fa2, zero + fmv.d.x fa3, zero + fmv.d.x fa4, zero + fmv.d.x fa5, zero + + # preload P from k=0, advance to k=1 + fld fa0, 0(t3) + fld fa1, 8(t3) + fld fa6, 16(t3) + fld fa7, 24(t3) + fld fs0, 0(t4) + fld fs1, 8(t4) + fld fs2, 16(t4) + fld fs3, 24(t4) + addi t3, t3, 32 + addi t4, t4, 32 + srli t6, a2, 1 # bk/2 + addi t6, t6, -1 # pair-cnt = bk/2 - 1 + beqz t6, .Lepi + + .p2align 4 +.Lbody: # --- P current, load Q (load before paired fmadd) --- + fld fs4, 0(t3) + fmadd.d ft0, fa0, fs0, ft0 + fld fs5, 8(t3) + fmadd.d ft1, fa1, fs0, ft1 + fld fs6, 16(t3) + fmadd.d ft2, fa6, fs0, ft2 + fld fs7, 24(t3) + fmadd.d ft3, fa7, fs0, ft3 + fld fs8, 0(t4) + fmadd.d ft4, fa0, fs1, ft4 + fld fs9, 8(t4) + fmadd.d ft5, fa1, fs1, ft5 + fld fs10, 16(t4) + fmadd.d ft6, fa6, fs1, ft6 + fld fs11, 24(t4) + fmadd.d ft7, fa7, fs1, ft7 + addi t3, t3, 32 + fmadd.d ft8, fa0, fs2, ft8 + addi t4, t4, 32 + fmadd.d ft9, fa1, fs2, ft9 + fmadd.d ft10, fa6, fs2, ft10 + fmadd.d ft11, fa7, fs2, ft11 + fmadd.d fa2, fa0, fs3, fa2 + fmadd.d fa3, fa1, fs3, fa3 + fmadd.d fa4, fa6, fs3, fa4 + fmadd.d fa5, fa7, fs3, fa5 + # --- Q current, load P --- + fld fa0, 0(t3) + fmadd.d ft0, fs4, fs8, ft0 + fld fa1, 8(t3) + fmadd.d ft1, fs5, fs8, ft1 + fld fa6, 16(t3) + fmadd.d ft2, fs6, fs8, ft2 + fld fa7, 24(t3) + fmadd.d ft3, fs7, fs8, ft3 + fld fs0, 0(t4) + fmadd.d ft4, fs4, fs9, ft4 + fld fs1, 8(t4) + fmadd.d ft5, fs5, fs9, ft5 + fld fs2, 16(t4) + fmadd.d ft6, fs6, fs9, ft6 + fld fs3, 24(t4) + fmadd.d ft7, fs7, fs9, ft7 + addi t3, t3, 32 + fmadd.d ft8, fs4, fs10, ft8 + addi t4, t4, 32 + fmadd.d ft9, fs5, fs10, ft9 + fmadd.d ft10, fs6, fs10, ft10 + fmadd.d ft11, fs7, fs10, ft11 + fmadd.d fa2, fs4, fs11, fa2 + fmadd.d fa3, fs5, fs11, fa3 + fmadd.d fa4, fs6, fs11, fa4 + fmadd.d fa5, fs7, fs11, fa5 + addi t6, t6, -1 + bnez t6, .Lbody + +.Lepi: # --- P current, load last Q --- + fld fs4, 0(t3) + fmadd.d ft0, fa0, fs0, ft0 + fld fs5, 8(t3) + fmadd.d ft1, fa1, fs0, ft1 + fld fs6, 16(t3) + fmadd.d ft2, fa6, fs0, ft2 + fld fs7, 24(t3) + fmadd.d ft3, fa7, fs0, ft3 + fld fs8, 0(t4) + fmadd.d ft4, fa0, fs1, ft4 + fld fs9, 8(t4) + fmadd.d ft5, fa1, fs1, ft5 + fld fs10, 16(t4) + fmadd.d ft6, fa6, fs1, ft6 + fld fs11, 24(t4) + fmadd.d ft7, fa7, fs1, ft7 + addi t3, t3, 32 + fmadd.d ft8, fa0, fs2, ft8 + addi t4, t4, 32 + fmadd.d ft9, fa1, fs2, ft9 + fmadd.d ft10, fa6, fs2, ft10 + fmadd.d ft11, fa7, fs2, ft11 + fmadd.d fa2, fa0, fs3, fa2 + fmadd.d fa3, fa1, fs3, fa3 + fmadd.d fa4, fa6, fs3, fa4 + fmadd.d fa5, fa7, fs3, fa5 + # --- Q current, compute only --- + fmadd.d ft0, fs4, fs8, ft0 + fmadd.d ft1, fs5, fs8, ft1 + fmadd.d ft2, fs6, fs8, ft2 + fmadd.d ft3, fs7, fs8, ft3 + fmadd.d ft4, fs4, fs9, ft4 + fmadd.d ft5, fs5, fs9, ft5 + fmadd.d ft6, fs6, fs9, ft6 + fmadd.d ft7, fs7, fs9, ft7 + fmadd.d ft8, fs4, fs10, ft8 + fmadd.d ft9, fs5, fs10, ft9 + fmadd.d ft10, fs6, fs10, ft10 + fmadd.d ft11, fs7, fs10, ft11 + fmadd.d fa2, fs4, fs11, fa2 + fmadd.d fa3, fs5, fs11, fa3 + fmadd.d fa4, fs6, fs11, fa4 + fmadd.d fa5, fs7, fs11, fa5 + + # ---- C += acc*alpha ; alpha->fs4, temps fs0/fs1 ---- + fld fs4, 96(sp) + fld fs0, 0(a0) + fmadd.d fs0, ft0, fs4, fs0 + fsd fs0, 0(a0) + fld fs1, 8(a0) + fmadd.d fs1, ft1, fs4, fs1 + fsd fs1, 8(a0) + fld fs0, 16(a0) + fmadd.d fs0, ft2, fs4, fs0 + fsd fs0, 16(a0) + fld fs1, 24(a0) + fmadd.d fs1, ft3, fs4, fs1 + fsd fs1, 24(a0) + fld fs0, 0(a1) + fmadd.d fs0, ft4, fs4, fs0 + fsd fs0, 0(a1) + fld fs1, 8(a1) + fmadd.d fs1, ft5, fs4, fs1 + fsd fs1, 8(a1) + fld fs0, 16(a1) + fmadd.d fs0, ft6, fs4, fs0 + fsd fs0, 16(a1) + fld fs1, 24(a1) + fmadd.d fs1, ft7, fs4, fs1 + fsd fs1, 24(a1) + fld fs0, 0(a6) + fmadd.d fs0, ft8, fs4, fs0 + fsd fs0, 0(a6) + fld fs1, 8(a6) + fmadd.d fs1, ft9, fs4, fs1 + fsd fs1, 8(a6) + fld fs0, 16(a6) + fmadd.d fs0, ft10, fs4, fs0 + fsd fs0, 16(a6) + fld fs1, 24(a6) + fmadd.d fs1, ft11, fs4, fs1 + fsd fs1, 24(a6) + fld fs0, 0(a7) + fmadd.d fs0, fa2, fs4, fs0 + fsd fs0, 0(a7) + fld fs1, 8(a7) + fmadd.d fs1, fa3, fs4, fs1 + fsd fs1, 8(a7) + fld fs0, 16(a7) + fmadd.d fs0, fa4, fs4, fs0 + fsd fs0, 16(a7) + fld fs1, 24(a7) + fmadd.d fs1, fa5, fs4, fs1 + fsd fs1, 24(a7) + + addi a0, a0, 32 + addi a1, a1, 32 + addi a6, a6, 32 + addi a7, a7, 32 + addi t5, t5, -1 + bnez t5, .Li + + slli t6, a2, 5 # bb(run) += bk*4 + add a4, a4, t6 + slli t6, t0, 2 # C(run) += 4*ldc + add a5, a5, t6 + addi t2, t2, -1 + bnez t2, .Lj + +.Ldone: + fld fs0, 0(sp) + fld fs1, 8(sp) + fld fs2, 16(sp) + fld fs3, 24(sp) + fld fs4, 32(sp) + fld fs5, 40(sp) + fld fs6, 48(sp) + fld fs7, 56(sp) + fld fs8, 64(sp) + fld fs9, 72(sp) + fld fs10, 80(sp) + fld fs11, 88(sp) + addi sp, sp, 112 + li a0, 0 + ret + .size kern_asm, .-kern_asm diff --git a/kernel/riscv64/KERNEL.U74 b/kernel/riscv64/KERNEL.U74 index c19d71d4af..c6cac398e0 100644 --- a/kernel/riscv64/KERNEL.U74 +++ b/kernel/riscv64/KERNEL.U74 @@ -109,7 +109,7 @@ SGEMMOTCOPY = ../generic/gemm_tcopy_4.c SGEMMONCOPYOBJ = sgemm_oncopy$(TSUFFIX).$(SUFFIX) SGEMMOTCOPYOBJ = sgemm_otcopy$(TSUFFIX).$(SUFFIX) -DGEMMKERNEL = ../generic/gemmkernel_4x4.c +DGEMMKERNEL = ../generic/gemmkernel_4x4_u74.c DGEMMONCOPY = ../generic/gemm_ncopy_4.c DGEMMOTCOPY = ../generic/gemm_tcopy_4.c DGEMMONCOPYOBJ = dgemm_oncopy$(TSUFFIX).$(SUFFIX) From cfdaa69b9fb2fe5fab256e6d82f5d1f7786dfd3a Mon Sep 17 00:00:00 2001 From: hmeiland Date: Fri, 10 Jul 2026 05:44:15 +0200 Subject: [PATCH 5/6] U74 asm kernel: note full-memory HPL result in header Full-memory HPL N=27456 (asm hybrid + Q=256) measured at 5.99 GFLOPS (residual PASSED, ~50% of the 12 GF peak, +10.7% over the tuned C kernel, 1.81x the stock 2x2) - the best clean figure. Doc-only header update. --- kernel/generic/gemmkernel_4x4_u74.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/kernel/generic/gemmkernel_4x4_u74.c b/kernel/generic/gemmkernel_4x4_u74.c index 42fe108ce0..73eed1a57e 100644 --- a/kernel/generic/gemmkernel_4x4_u74.c +++ b/kernel/generic/gemmkernel_4x4_u74.c @@ -54,9 +54,10 @@ * double-buffering (P/Q ping-pong) and load-before-FMA issue ordering that * reaches the U74 FP-pipe peak (~16.5 cycles per 16 fmadd.d). All other * shapes, odd bk, and the TRMM builds fall back to the portable C 4x4 code - * below. Measured ~+20% single-core DGEMM and +4% four-core HPL over the C - * kernel; validated against the full BLAS Level-3 suite (DGEMM 17,496 calls, - * 0 failures) and HPL (residual PASSED). + * below. Measured ~+20% single-core DGEMM over the C kernel; four-core HPL vs + * the tuned C kernel is +4% at N=10000 and +10.7% at N=27456 (5.99 GFLOPS, + * ~50% of the 12 GF peak - the best clean figure). Validated against the full + * BLAS Level-3 suite (DGEMM 17,496 calls, 0 failures) and HPL (residual PASSED). */ #include "common.h" From d6e64e8032e608584fb21397afd9df26a3f91d16 Mon Sep 17 00:00:00 2001 From: hmeiland Date: Fri, 10 Jul 2026 06:36:10 +0200 Subject: [PATCH 6/6] U74 target: add CMake build support Mirror the RISCV64_GENERIC target blocks for U74 in cmake/prebuild.cmake (cache defines: 32 KiB L1D / 2 MiB L2, 64 B lines, matching getarch), cmake/system.cmake and cmake/cc.cmake (-march=rv64imafdc_zba_zbb -mabi=lp64d -mtune=sifive-u74), so 'cmake -DTARGET=U74' builds alongside the Makefile path. Verified on a VisionFive 2: configure recognizes the target and a full 'cmake --build' produces libopenblas.a with the U74 march/mtune flags applied to the kernel objects (0 errors). --- cmake/cc.cmake | 3 +++ cmake/prebuild.cmake | 9 +++++++++ cmake/system.cmake | 3 +++ 3 files changed, 15 insertions(+) diff --git a/cmake/cc.cmake b/cmake/cc.cmake index bacdbef5af..0ffe15c025 100644 --- a/cmake/cc.cmake +++ b/cmake/cc.cmake @@ -428,6 +428,9 @@ endif() if (${CORE} STREQUAL RISCV64_GENERIC) set (CCOMMON_OPT "${CCOMMON_OPT} -march=rv64imafdc -mabi=lp64d") endif() +if (${CORE} STREQUAL U74) + set (CCOMMON_OPT "${CCOMMON_OPT} -march=rv64imafdc_zba_zbb -mabi=lp64d -mtune=sifive-u74") +endif() if (${CORE} STREQUAL x280) set (CCOMMON_OPT "${CCOMMON_OPT} -march=rv64imafdcv_zba_zbb_zfh_zvl512b -mabi=lp64d") endif() diff --git a/cmake/prebuild.cmake b/cmake/prebuild.cmake index 827c2ba69b..efee778604 100644 --- a/cmake/prebuild.cmake +++ b/cmake/prebuild.cmake @@ -1504,6 +1504,15 @@ endif () "#define DTB_DEFAULT_ENTRIES 128\n" "#define DTB_SIZE 4096\n" "#define L2_ASSOCIATIVE 4\n") + elseif ("${TCORE}" STREQUAL "U74") + file(APPEND ${TARGET_CONF_TEMP} + "#define L1_DATA_SIZE 32768\n" + "#define L1_DATA_LINESIZE 64\n" + "#define L2_SIZE 2097152\n" + "#define L2_LINESIZE 64 \n" + "#define DTB_DEFAULT_ENTRIES 128\n" + "#define DTB_SIZE 4096\n" + "#define L2_ASSOCIATIVE 16\n") elseif ("${TCORE}" STREQUAL "WASM128_GENERIC") file(APPEND ${TARGET_CONF_TEMP} "#define L1_DATA_SIZE 32768\n" diff --git a/cmake/system.cmake b/cmake/system.cmake index 71bd1142c6..428455c8a9 100644 --- a/cmake/system.cmake +++ b/cmake/system.cmake @@ -409,6 +409,9 @@ if (${TARGET} STREQUAL NEOVERSEV1) if (${TARGET} STREQUAL RISCV64_GENERIC) set (KERNEL_DEFINITIONS "${KERNEL_DEFINITIONS} -march=rv64imafdc -mabi=lp64d") endif() + if (${TARGET} STREQUAL U74) + set (KERNEL_DEFINITIONS "${KERNEL_DEFINITIONS} -march=rv64imafdc_zba_zbb -mabi=lp64d -mtune=sifive-u74") + endif() if (${TARGET} STREQUAL x280) set (KERNEL_DEFINITIONS "${KERNEL_DEFINITIONS} -march=rv64imafdcv_zba_zbb_zfh_zvl512b -mabi=lp64d") endif()