TAG SRAM uses excessive BRAM in FPGA target

[thomas6785]

In axi_sram.sv there is a RAM primitive instantiated for tag storage:

  // Tag RAM
  prim_ram_1p #(
    .Width           ( top_pkg::AxiDataWidth ),
    .DataBitsPerMask ( 1                     ),
    .Depth           ( 2 ** TagAddrWidth     )
  ) u_tag_ram (
    .clk_i  (clk_i),
    .rst_ni (rst_ni),

    .req_i   (sram_req),
    .write_i (sram_we_d),
    .addr_i  (sram_tag_word_addr),
    .wdata_i (sram_tag_wdata),
    .wmask_i (sram_tag_wmask),
    .rdata_o (sram_tag_rdata),

    .cfg_i     ('0),
    .cfg_rsp_o ( )
  );

Each tag is only one bit so the memory needs to be writeable with one-bit granularity
However the Xilinx FPGA primitives do not accommodate this, so the synthesis tool infers a separate BRAM instance for each bit of width
Consequently the tag SRAM uses equal resources to the main SRAM memory:

(2 BRAM18 = 1 BRAM36)
It would be expected the tag storage represent a small fraction of overall storage, not 50%

This does not affect ASIC implementations