From b5fc7cd724632dc7e47bc963fcd0dd066288059b Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:37 +0530 Subject: [PATCH 01/36] FROMLIST: ARM: dts: qcom: sdx55: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-1-2744251b1181@oss.qualcomm.com/ --- arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts index 082f7ed1a01fb..302c88c479604 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts +++ b/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts @@ -251,7 +251,7 @@ &pcie_rc { perst-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie_default>; pinctrl-names = "default"; From cafc3191e04ba80d5bd929a0133a24acc865e434 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:38 +0530 Subject: [PATCH 02/36] FROMLIST: arm64: dts: qcom: msm8996: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-2-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi index d55e4075040ff..5b42c266557ab 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi @@ -192,7 +192,7 @@ &pcie0 { perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&wlan_en>; vdda-supply = <&pm8994_l28>; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 0386636a29f05..337db4db9895a 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -280,7 +280,7 @@ vdda-supply = <&vreg_l28a_0p925>; perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; }; &pcie_phy { From 9017a9675ee525f55c5d7232dd95e8ec176e75e1 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:39 +0530 Subject: [PATCH 03/36] FROMLIST: arm64: dts: qcom: sdm845: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-3-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 5147d6d3cc26b..cd3c1cf047f9c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -582,7 +582,7 @@ &pcie0 { status = "okay"; perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 134 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 134 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&pcie0_3p3v_dual>; From 91ce58fd172787657c87213d6cf64e5bf5066920 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:40 +0530 Subject: [PATCH 04/36] FROMLIST: arm64: dts: qcom: sc8180x: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-4-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 2 +- arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 08d0784d0cbb8..acea9b1460391 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -464,7 +464,7 @@ &pcie3 { perst-gpios = <&tlmm 178 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 180 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 180 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie3_default_state>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts index 93de9fe918ebd..1b9f239931d9a 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -558,7 +558,7 @@ &pcie1 { perst-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 177 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 177 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie2_default_state>; From 918c1c8bb3d3a70fcdd6468255b8b732f7c73eb1 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:41 +0530 Subject: [PATCH 05/36] FROMLIST: arm64: dts: qcom: sm8150: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-5-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index acdba79612aa8..a9840c23b8c2a 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1896,7 +1896,7 @@ phy-names = "pciephy"; perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; - wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; From 1d4bdcaeb42e752ec659da78527120ba8516b91c Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:42 +0530 Subject: [PATCH 06/36] FROMLIST: arm64: dts: qcom: sm8250: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-6-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 50dd11432bb2e..defbe6608efdf 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2197,7 +2197,7 @@ phy-names = "pciephy"; perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 81 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; @@ -2324,7 +2324,7 @@ phy-names = "pciephy"; perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 84 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; @@ -2451,7 +2451,7 @@ phy-names = "pciephy"; perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie2_default_state>; From 18961e4a6a48630f06cb74dbc5f5a4e4e71ed153 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:43 +0530 Subject: [PATCH 07/36] FROMLIST: arm64: dts: qcom: sm8350: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-7-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 24a8c91e9f70f..95733ccca9abe 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -494,7 +494,7 @@ pinctrl-0 = <&pcie0_default_state>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -508,7 +508,7 @@ &pcie1 { perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; From 10e339347852783fa8fd742e02254401bb0eb804 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:44 +0530 Subject: [PATCH 08/36] FROMLIST: arm64: dts: qcom: sm8450: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-8-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index cdaff13325ccb..a8f2c412e687e 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2035,7 +2035,7 @@ phy-names = "pciephy"; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; @@ -2197,7 +2197,7 @@ phy-names = "pciephy"; perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; From ef06f059e721331061734d054fae1f95cad186ff Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:45 +0530 Subject: [PATCH 09/36] FROMLIST: arm64: dts: qcom: sm8550: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-9-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 2 +- arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts | 2 +- arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 2 +- 6 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi index e6ac529e6b721..ca32e9eda5d44 100644 --- a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi @@ -336,7 +336,7 @@ &pcie0 { perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -349,7 +349,7 @@ &pcie1 { perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_default_state>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index b5d7f0cd443a1..d3b31f654a135 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -1003,7 +1003,7 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; @@ -1037,7 +1037,7 @@ }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_default_state>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 38f2928f23cc3..5a35eb659aea7 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -739,7 +739,7 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -756,7 +756,7 @@ }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index a3f4200a1145d..a050ad18123de 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -858,7 +858,7 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts index b4ef40ae2cd95..8b672939791a9 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts @@ -510,7 +510,7 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts index d90dc7b37c4a7..8a484489ad731 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts @@ -584,7 +584,7 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; From 02fbf8ed5a10a0d4dd7786e1c0a2b4580d6c6d54 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:46 +0530 Subject: [PATCH 10/36] FROMLIST: arm64: dts: qcom: sm8650: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-10-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts index 0dc994f4e48d9..2123312d88f6b 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts @@ -1074,7 +1074,7 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; @@ -1108,7 +1108,7 @@ }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_default_state>; diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index 87d7190dc991b..92b10ba13710b 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -942,7 +942,7 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; @@ -976,7 +976,7 @@ }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_default_state>; diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index c67bbace27439..8dc24db239bb5 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -642,7 +642,7 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; @@ -659,7 +659,7 @@ }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_default_state>; diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index 9e790cf44804d..70b3f0c4b6e3e 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -893,7 +893,7 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; From b87c2b0370ff230af4bc4c3f2adc9b8eb87bd762 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:47 +0530 Subject: [PATCH 11/36] FROMLIST: arm64: dts: qcom: sm8750: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-11-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts index 9b8c453b6fe2b..dd939dc12bd51 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts @@ -974,7 +974,7 @@ }; &pcieport0 { - wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 104 GPIO_ACTIVE_LOW>; reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; wifi@0 { From 70d07bfc9e611994f0df390c97dc5bdd0b25a6c1 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:49 +0530 Subject: [PATCH 12/36] FROMLIST: arm64: dts: qcom: sar2130p: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-13-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts b/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts index 74778a5b19ba6..71a09e76b3592 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts +++ b/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts @@ -358,7 +358,7 @@ &pcie0 { perst-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; From d2e9a8348ab810fdf38c08ddac2fb2bd4e837bae Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:50 +0530 Subject: [PATCH 13/36] FROMLIST: arm64: dts: qcom: monaco: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-14-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/monaco-evk-common.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-common.dtsi b/arch/arm64/boot/dts/qcom/monaco-evk-common.dtsi index 2434d1f9f58ba..92822ba5f48c5 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk-common.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco-evk-common.dtsi @@ -734,12 +734,12 @@ &pcieport0 { reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; }; &pcieport1 { reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 21 GPIO_ACTIVE_LOW>; }; &pmm8620au_0_gpios { diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index 4e2fb94a147c5..842aa6743ef75 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -597,7 +597,7 @@ &pcieport0 { reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; }; &pcie0_phy { @@ -617,7 +617,7 @@ &pcieport1 { reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 21 GPIO_ACTIVE_LOW>; }; &pcie1_phy { From 159d8361d655f0555865e5c5752a0a6dc9da2d9e Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:51 +0530 Subject: [PATCH 14/36] FROMLIST: arm64: dts: qcom: lemans: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-15-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 4 ++-- arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index eec8b8a1d9ae8..255718355fcaf 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -834,7 +834,7 @@ &pcie0 { perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -851,7 +851,7 @@ &pcie1 { perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_default_state>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi index d66b33a1812ca..ca3031dc5cef8 100644 --- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi @@ -969,7 +969,7 @@ &pcie0 { perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; @@ -979,7 +979,7 @@ &pcie1 { perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; From b3a88fc58738de3d7707de63dab983a28e61e67f Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:52 +0530 Subject: [PATCH 15/36] FROMLIST: arm64: dts: qcom: sa8540p-ride: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-16-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index 44177e9b64b52..702ae4cd3d0c1 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -367,7 +367,7 @@ <0x03000000 0x5 0x00000000 0x5 0x00000000 0x1 0x00000000>; perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie2a_default>; @@ -388,7 +388,7 @@ <0x03000000 0x6 0x00000000 0x6 0x00000000 0x2 0x00000000>; perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie3a_default>; From 8f99ada32c7ed27a46e87cbb7c497a54de86ba27 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:53 +0530 Subject: [PATCH 16/36] FROMLIST: arm64: dts: qcom: kodiak: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-17-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts index c8494a9254fcd..ba01677f64cb3 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts @@ -550,7 +550,7 @@ &pcie0 { perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>; pinctrl-names = "default"; From 10c0326db34eb72a4fa78114810ee29b64503f26 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:54 +0530 Subject: [PATCH 17/36] FROMLIST: arm64: dts: qcom: talos: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-18-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 2 +- arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index 570ce3ddc4b0c..ddf94d6b39ca9 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -524,7 +524,7 @@ &pcie { perst-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie_default_state>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi index c5da6858b74b1..71095874d65e9 100644 --- a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi +++ b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi @@ -443,7 +443,7 @@ &pcie { perst-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie_default_state>; pinctrl-names = "default"; From 441ba0089a1741c7de404db5d6d662a90dc11a4f Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:55 +0530 Subject: [PATCH 18/36] FROMLIST: arm64: dts: qcom: lemans: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys from the controller to pcieport0 and pcieport1. Add the missing pcieport1 label to the pcie1 root port node to allow board-level overrides. Move perst-gpios/wake-gpios from the &pcie0/&pcie1 controller overrides to the respective &pcieport0/ &pcieport1 nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-19-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 16 ++++++++++------ arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi | 16 ++++++++++------ arch/arm64/boot/dts/qcom/lemans.dtsi | 12 +++++------- 3 files changed, 25 insertions(+), 19 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index 255718355fcaf..3403f8c6d3057 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -833,15 +833,17 @@ }; &pcie0 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcieport0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l5a>; vdda-pll-supply = <&vreg_l1c>; @@ -850,15 +852,17 @@ }; &pcie1 { - perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcieport1 { + reset-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { vdda-phy-supply = <&vreg_l5a>; vdda-pll-supply = <&vreg_l1c>; diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi index ca3031dc5cef8..8781c43b2f822 100644 --- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi @@ -968,25 +968,29 @@ }; &pcie0 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; status = "okay"; }; -&pcie1 { - perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; +&pcieport0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; +}; +&pcie1 { pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; status = "okay"; }; +&pcieport1 { + reset-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l5a>; vdda-pll-supply = <&vreg_l1c>; diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 5cff6bb90f407..adf807bfbdae4 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -8989,9 +8989,6 @@ power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; eq-presets-16gts = /bits/ 8 <0x55 0x55>; @@ -9002,6 +8999,8 @@ reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie0_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -9162,19 +9161,18 @@ power-domains = <&gcc PCIE_1_GDSC>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; status = "disabled"; - pcie@0 { + pcieport1: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie1_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; From 4aab3ab4bed893feedf507abbc9caf3d18fbf0c7 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:56 +0530 Subject: [PATCH 19/36] FROMLIST: arm64: dts: qcom: msm8998: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst GPIO property are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys, phy-names, and perst-gpios from the controller to pcie0_port0, adding a label to this node to allow board-level overrides, and renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-20-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 5c75fba16ce2c..cbddb77a7a03a 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -928,8 +928,6 @@ #address-cells = <3>; #size-cells = <2>; num-lanes = <1>; - phys = <&pcie_phy>; - phy-names = "pciephy"; status = "disabled"; ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>, @@ -969,9 +967,8 @@ power-domains = <&gcc PCIE_0_GDSC>; iommu-map = <0x100 &anoc1_smmu 0x1480 1>; - perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -979,6 +976,9 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie_phy>; + reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; }; }; From e4b5e07f4481b9c9efa070844e5350b32c156fea Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:57 +0530 Subject: [PATCH 20/36] FROMLIST: arm64: dts: qcom: qcs404: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst GPIO property are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to pcie0_port0, adding a label to this node to allow board-level overrides. Move perst-gpios from the &pcie controller override to &pcie0_port0 in the board file, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-21-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 6 ++++-- arch/arm64/boot/dts/qcom/qcs404.dtsi | 7 +++---- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index a22b4501ce1ef..a035546a1b97d 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -101,12 +101,14 @@ &pcie { status = "okay"; - perst-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&perst_state>; }; +&pcie0_port0 { + reset-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>; +}; + &pcie_phy { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 4328c1dda898c..8166ab4bf01cf 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -1517,12 +1517,9 @@ "pwr", "ahb"; - phys = <&pcie_phy>; - phy-names = "pciephy"; - status = "disabled"; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -1530,6 +1527,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie_phy>; }; }; }; From 9946df2536803c251750c40d0022f3ccba7927a1 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:58 +0530 Subject: [PATCH 21/36] FROMLIST: arm64: dts: qcom: qcs8550: Move PCIe GPIOs to root port node The perst/wake GPIO properties are per root port and belong in the root port node, not in the RC controller node. Move perst-gpios/ wake-gpios from the &pcie0/&pcie1 controller overrides to the respective &pcieport0/&pcie1_port0 nodes, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-22-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi index ca32e9eda5d44..29b247324a429 100644 --- a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi @@ -335,26 +335,30 @@ }; &pcie0 { - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; }; +&pcieport0 { + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l1e_0p88>; vdda-pll-supply = <&vreg_l3e_1p2>; }; &pcie1 { - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_default_state>; pinctrl-names = "default"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { vdda-phy-supply = <&vreg_l3c_0p9>; vdda-pll-supply = <&vreg_l3e_1p2>; From af0f30ce277757773e67c12eeb46e233e0ad4279 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:59 +0530 Subject: [PATCH 22/36] FROMLIST: arm64: dts: qcom: sa8295p: Move PCIe GPIOs to root port node The perst/wake GPIO properties are per root port and belong in the root port node, not in the RC controller node. Move perst-gpios/ wake-gpios from the &pcie2a, &pcie3a, &pcie3b, and &pcie4 controller overrides to the respective &pcie2a_port0, &pcie3a_port0, &pcie3b_port0, and &pcie4_port0 nodes, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-23-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 32 +++++++++++++++--------- 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index 64e59299672cb..e4e03711cc098 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -461,15 +461,17 @@ }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie2a_default>; status = "okay"; }; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + &pcie2a_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; @@ -480,15 +482,17 @@ &pcie3a { num-lanes = <2>; - perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie3a_default>; status = "okay"; }; +&pcie3a_port0 { + reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>; +}; + &pcie3a_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; @@ -497,15 +501,17 @@ }; &pcie3b { - perst-gpios = <&tlmm 153 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie3b_default>; status = "okay"; }; +&pcie3b_port0 { + reset-gpios = <&tlmm 153 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>; +}; + &pcie3b_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; @@ -514,15 +520,17 @@ }; &pcie4 { - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie4_default>; status = "okay"; }; +&pcie4_port0 { + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; +}; + &pcie4_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; From a72eb6e25815935805e5ddc3fcb7740a52e0594f Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:00 +0530 Subject: [PATCH 23/36] FROMLIST: arm64: dts: qcom: sa8540p: Move PCIe GPIOs to root port node The perst/wake GPIO properties are per root port and belong in the root port node, not in the RC controller node. Move perst-gpios/ wake-gpios from the &pcie2a and &pcie3a controller overrides to the respective &pcie2a_port0 and &pcie3a_port0 nodes, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-24-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index 702ae4cd3d0c1..6e73fca4e1bfc 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -366,15 +366,17 @@ <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>, <0x03000000 0x5 0x00000000 0x5 0x00000000 0x1 0x00000000>; - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie2a_default>; status = "disabled"; }; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + &pcie2a_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; @@ -387,15 +389,17 @@ <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x20000000>, <0x03000000 0x6 0x00000000 0x6 0x00000000 0x2 0x00000000>; - perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie3a_default>; status = "okay"; }; +&pcie3a_port0 { + reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>; +}; + &pcie3a_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; From e6d4c4c1aceaacbec5b124062c68e103744524f6 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:01 +0530 Subject: [PATCH 24/36] FROMLIST: arm64: dts: qcom: sar2130p: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to the existing pcieport0 and newly labeled pcie1_port0, allowing board-level overrides. Move perst-gpios/wake-gpios from the &pcie0 controller override to &pcieport0 in the board file, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-25-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts | 6 +++--- arch/arm64/boot/dts/qcom/sar2130p.dtsi | 12 +++++------- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts b/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts index 71a09e76b3592..6e0557f1c14b9 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts +++ b/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts @@ -357,9 +357,6 @@ }; &pcie0 { - perst-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -367,6 +364,9 @@ }; &pcieport0 { + reset-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi index d65ad0df68652..804ccfbdb0918 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi @@ -1337,9 +1337,6 @@ power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - status = "disabled"; pcieport0: pcie@0 { @@ -1350,6 +1347,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie0_phy>; }; }; @@ -1464,12 +1463,9 @@ power-domains = <&gcc PCIE_1_GDSC>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -1477,6 +1473,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie1_phy>; }; }; From 155bafe388dc6c85b02cd42f860fb8b08ffce002 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:02 +0530 Subject: [PATCH 25/36] FROMLIST: arm64: dts: qcom: sc8180x: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to pcie0_port0, pcie1_port0, pcie2_port0, and pcie3_port0, adding labels to these nodes to allow board-level overrides. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-26-2744251b1181@oss.qualcomm.com/ --- .../boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 7 ++++-- arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 7 ++++-- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 24 +++++++++---------- 3 files changed, 22 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index acea9b1460391..3fd377188dcf5 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -463,14 +463,17 @@ }; &pcie3 { - perst-gpios = <&tlmm 178 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 180 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie3_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcie3_port0 { + reset-gpios = <&tlmm 178 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 180 GPIO_ACTIVE_LOW>; +}; + &pcie3_phy { vdda-phy-supply = <&vreg_l5e_0p88>; vdda-pll-supply = <&vreg_l3c_1p2>; diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts index 1b9f239931d9a..297b973ba1ad6 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -557,14 +557,17 @@ }; &pcie1 { - perst-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 177 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie2_default_state>; status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 177 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { vdda-phy-supply = <&vreg_l5e_0p88>; vdda-pll-supply = <&vreg_l3c_1p2>; diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 85c2afcb417de..218fa66adb2ca 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -1774,13 +1774,11 @@ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; interconnect-names = "pcie-mem", "cpu-pcie"; - phys = <&pcie0_phy>; - phy-names = "pciephy"; dma-coherent; status = "disabled"; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -1788,6 +1786,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie0_phy>; }; }; @@ -1893,13 +1893,11 @@ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_3 0>; interconnect-names = "pcie-mem", "cpu-pcie"; - phys = <&pcie3_phy>; - phy-names = "pciephy"; dma-coherent; status = "disabled"; - pcie@0 { + pcie3_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -1907,6 +1905,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie3_phy>; }; }; @@ -2013,13 +2013,11 @@ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_1 0>; interconnect-names = "pcie-mem", "cpu-pcie"; - phys = <&pcie1_phy>; - phy-names = "pciephy"; dma-coherent; status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2027,6 +2025,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie1_phy>; }; }; @@ -2133,13 +2133,11 @@ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_2 0>; interconnect-names = "pcie-mem", "cpu-pcie"; - phys = <&pcie2_phy>; - phy-names = "pciephy"; dma-coherent; status = "disabled"; - pcie@0 { + pcie2_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2147,6 +2145,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie2_phy>; }; }; From 4bba072e5cb854eae4fb8065402f3571d7f82d6e Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:03 +0530 Subject: [PATCH 26/36] FROMLIST: arm64: dts: qcom: sc8280xp: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to the existing pcie2a_port0, pcie2b_port0, pcie3a_port0, pcie3b_port0, and pcie4_port0 nodes. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-27-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 24 +++++++++++------- .../boot/dts/qcom/sc8280xp-huawei-gaokun3.dts | 14 ++++++----- .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 22 +++++++++------- .../dts/qcom/sc8280xp-microsoft-arcata.dts | 22 +++++++++------- .../dts/qcom/sc8280xp-microsoft-blackrock.dts | 14 ++++++----- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 25 ++++++++----------- 6 files changed, 67 insertions(+), 54 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 490e970c54a24..960eb90ca0893 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -634,9 +634,6 @@ }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-names = "default"; @@ -645,6 +642,11 @@ status = "okay"; }; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + &pcie2a_phy { vdda-phy-supply = <&vreg_l6d>; vdda-pll-supply = <&vreg_l4d>; @@ -653,9 +655,6 @@ }; &pcie3a { - perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_wwan>; pinctrl-names = "default"; @@ -664,6 +663,11 @@ status = "okay"; }; +&pcie3a_port0 { + reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +}; + &pcie3a_phy { vdda-phy-supply = <&vreg_l6d>; vdda-pll-supply = <&vreg_l4d>; @@ -674,9 +678,6 @@ &pcie4 { max-link-speed = <2>; - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_wlan>; pinctrl-names = "default"; @@ -685,6 +686,11 @@ status = "okay"; }; +&pcie4_port0 { + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; +}; + &pcie4_phy { vdda-phy-supply = <&vreg_l6d>; vdda-pll-supply = <&vreg_l4d>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts index 0374251d33291..0e4cccb246149 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts @@ -745,9 +745,6 @@ }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-0 = <&pcie2a_default>; @@ -756,6 +753,11 @@ status = "okay"; }; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + &pcie2a_phy { vdda-phy-supply = <&vreg_l6d>; vdda-pll-supply = <&vreg_l4d>; @@ -766,9 +768,6 @@ &pcie4 { max-link-speed = <2>; - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_wlan>; pinctrl-0 = <&pcie4_default>; @@ -778,6 +777,9 @@ }; &pcie4_port0 { + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1103"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 637430719e6d7..26ee3556e0dcc 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -939,9 +939,6 @@ }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-names = "default"; @@ -950,6 +947,11 @@ status = "okay"; }; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + &pcie2a_phy { vdda-phy-supply = <&vreg_l6d>; vdda-pll-supply = <&vreg_l4d>; @@ -958,9 +960,6 @@ }; &pcie3a { - perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_wwan>; pinctrl-names = "default"; @@ -969,6 +968,11 @@ status = "okay"; }; +&pcie3a_port0 { + reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +}; + &pcie3a_phy { vdda-phy-supply = <&vreg_l6d>; vdda-pll-supply = <&vreg_l4d>; @@ -979,9 +983,6 @@ &pcie4 { max-link-speed = <2>; - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_wlan>; pinctrl-names = "default"; @@ -991,6 +992,9 @@ }; &pcie4_port0 { + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1103"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts index aeed3ef152eba..663f9c8263e05 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts @@ -492,9 +492,6 @@ }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-0 = <&pcie2a_default>; @@ -503,6 +500,11 @@ status = "okay"; }; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + &pcie2a_phy { vdda-phy-supply = <&vreg_l6d>; vdda-pll-supply = <&vreg_l4d>; @@ -511,9 +513,6 @@ }; &pcie3a { - perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_wwan>; pinctrl-0 = <&pcie3a_default>; @@ -522,6 +521,11 @@ status = "okay"; }; +&pcie3a_port0 { + reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +}; + &pcie3a_phy { vdda-phy-supply = <&vreg_l6d>; vdda-pll-supply = <&vreg_l4d>; @@ -532,9 +536,6 @@ &pcie4 { max-link-speed = <2>; - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_wlan>; pinctrl-0 = <&pcie4_default>; @@ -544,6 +545,9 @@ }; &pcie4_port0 { + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1103"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts index a40dccd70dfda..2692063fe7545 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts @@ -630,9 +630,6 @@ }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-0 = <&pcie2a_default>; @@ -641,6 +638,11 @@ status = "okay"; }; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + &pcie2a_phy { vdda-phy-supply = <&vreg_l4d>; vdda-pll-supply = <&vreg_l6d>; @@ -651,9 +653,6 @@ &pcie4 { max-link-speed = <2>; - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_wlan>; pinctrl-0 = <&pcie4_default>; @@ -663,6 +662,9 @@ }; &pcie4_port0 { + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1103"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index d89938e17e093..8bf863308830b 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2214,9 +2214,6 @@ power-domains = <&gcc PCIE_4_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&pcie4_phy>; - phy-names = "pciephy"; - status = "disabled"; pcie4_port0: pcie@0 { @@ -2227,6 +2224,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie4_phy>; }; }; @@ -2325,9 +2324,6 @@ power-domains = <&gcc PCIE_3B_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&pcie3b_phy>; - phy-names = "pciephy"; - status = "disabled"; pcie3b_port0: pcie@0 { @@ -2338,6 +2334,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie3b_phy>; }; }; @@ -2436,9 +2434,6 @@ power-domains = <&gcc PCIE_3A_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&pcie3a_phy>; - phy-names = "pciephy"; - status = "disabled"; pcie3a_port0: pcie@0 { @@ -2449,6 +2444,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie3a_phy>; }; }; @@ -2550,9 +2547,6 @@ power-domains = <&gcc PCIE_2B_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&pcie2b_phy>; - phy-names = "pciephy"; - status = "disabled"; pcie2b_port0: pcie@0 { @@ -2563,6 +2557,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie2b_phy>; }; }; @@ -2661,9 +2657,6 @@ power-domains = <&gcc PCIE_2A_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&pcie2a_phy>; - phy-names = "pciephy"; - status = "disabled"; pcie2a_port0: pcie@0 { @@ -2674,6 +2667,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie2a_phy>; }; }; From bcd455973770f238d6aaf55342b354534e9f4111 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:04 +0530 Subject: [PATCH 27/36] FROMLIST: arm64: dts: qcom: sdm845: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to pcie0_port0 and pcie1_port0, adding labels to these nodes to allow board-level overrides. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-28-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 13 +++++++++---- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 12 ++++++++---- arch/arm64/boot/dts/qcom/sdm845.dtsi | 14 ++++++-------- 3 files changed, 23 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index cd3c1cf047f9c..a15a6f131b872 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -581,15 +581,17 @@ &pcie0 { status = "okay"; - perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 134 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&pcie0_3p3v_dual>; pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; }; +&pcie0_port0 { + reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 134 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { status = "okay"; @@ -599,12 +601,15 @@ &pcie1 { status = "okay"; - perst-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; }; +&pcie1_port0 { + reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index 63d2993536ade..d9a4dcf1c83d7 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -511,14 +511,16 @@ }; &pcie0 { - perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcie0_port0 { + reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l1a_0p875>; vdda-pll-supply = <&vreg_l26a_1p2>; @@ -527,14 +529,16 @@ }; &pcie1 { - perst-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 13c9515260ef1..1a3276c6dde04 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2389,12 +2389,9 @@ power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - status = "disabled"; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2402,6 +2399,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie0_phy>; }; }; @@ -2519,12 +2518,9 @@ power-domains = <&gcc PCIE_1_GDSC>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2532,6 +2528,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie1_phy>; }; }; From c7d696288e90a0df9d4ddb1e570ed31a0cf51ba4 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:05 +0530 Subject: [PATCH 28/36] FROMLIST: arm64: dts: qcom: sm8150: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys, phy-names, perst-gpios, and wake-gpios from the controller to pcie0_port0 and pcie1_port0, adding labels to these nodes to allow board-level overrides, and renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-29-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index a9840c23b8c2a..3265786e05381 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1892,18 +1892,12 @@ power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - - perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; - wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; status = "disabled"; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -1911,6 +1905,10 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie0_phy>; + reset-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; }; }; @@ -2010,10 +2008,6 @@ power-domains = <&gcc PCIE_1_GDSC>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - - perst-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; @@ -2021,7 +2015,7 @@ status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2029,6 +2023,9 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie1_phy>; + reset-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; }; }; From 695ac83eee9106077cc80c3415f2a763dbdea80a Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:06 +0530 Subject: [PATCH 29/36] FROMLIST: arm64: dts: qcom: sm8250: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys, phy-names, perst-gpios, and wake-gpios from the controller to the existing pcieport0 and newly labeled pcie1_port0 and pcie2_port0, allowing board-level overrides. Rename perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-30-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 34 ++++++++++++---------------- 1 file changed, 14 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index defbe6608efdf..70bf9bad0b303 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2193,12 +2193,6 @@ power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - - perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 81 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; dma-coherent; @@ -2213,6 +2207,10 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie0_phy>; + reset-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 81 GPIO_ACTIVE_LOW>; }; }; @@ -2320,19 +2318,13 @@ power-domains = <&gcc PCIE_1_GDSC>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - - perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 84 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; dma-coherent; status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2340,6 +2332,10 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie1_phy>; + reset-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 84 GPIO_ACTIVE_LOW>; }; }; @@ -2447,19 +2443,13 @@ power-domains = <&gcc PCIE_2_GDSC>; - phys = <&pcie2_phy>; - phy-names = "pciephy"; - - perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie2_default_state>; dma-coherent; status = "disabled"; - pcie@0 { + pcie2_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2467,6 +2457,10 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie2_phy>; + reset-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; }; }; From 2e6ec9199457a4b01c6fbd50bca2cc691f587372 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:07 +0530 Subject: [PATCH 30/36] FROMLIST: arm64: dts: qcom: sm8350: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to pcie0_port0 and pcie1_port0, adding labels to these nodes to allow board-level overrides. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board file, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-31-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 16 ++++++++++------ arch/arm64/boot/dts/qcom/sm8350.dtsi | 14 ++++++-------- 2 files changed, 16 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 95733ccca9abe..eb4bfb8b6a89a 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -493,12 +493,14 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - status = "okay"; }; +&pcie0_port0 { + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l5b_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; @@ -507,15 +509,17 @@ }; &pcie1 { - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { status = "okay"; vdda-phy-supply = <&vreg_l5b_0p88>; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index fc4ce9d4977e8..7c1d398426e58 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1583,12 +1583,9 @@ power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - status = "disabled"; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -1596,6 +1593,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie0_phy>; }; }; @@ -1692,12 +1691,9 @@ power-domains = <&gcc PCIE_1_GDSC>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -1705,6 +1701,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie1_phy>; }; }; From cfae44c6714528fb61c1c7e70febd95576075094 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:08 +0530 Subject: [PATCH 31/36] FROMLIST: arm64: dts: qcom: sm8450: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys, phy-names, perst-gpios, and wake-gpios from the controller to the existing pcieport0 and newly labeled pcie1_port0, allowing board-level overrides. Rename perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-32-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index a8f2c412e687e..253330bc9bcf9 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2031,12 +2031,6 @@ power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; @@ -2077,6 +2071,10 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie0_phy>; + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; }; }; @@ -2193,12 +2191,6 @@ power-domains = <&gcc PCIE_1_GDSC>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; @@ -2252,7 +2244,7 @@ }; }; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2260,6 +2252,10 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie1_phy>; + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; }; }; From 041e5f16c8e35a187ac95b3bca76cfd08e6f7d95 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:09 +0530 Subject: [PATCH 32/36] FROMLIST: arm64: dts: qcom: sm8550: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to the existing pcieport0 and newly labeled pcie1_port0, allowing board-level overrides. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-33-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 14 ++++++++------ arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 16 ++++++++++------ arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 6 +++--- arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts | 7 +++++-- .../dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 8 +++++--- arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 +++++------- 6 files changed, 36 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index d3b31f654a135..17e087165a5d6 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -1003,9 +1003,6 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -1013,6 +1010,9 @@ }; &pcieport0 { + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; @@ -1037,15 +1037,17 @@ }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { vdda-phy-supply = <&vreg_l3c_0p9>; vdda-pll-supply = <&vreg_l3e_1p2>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 5a35eb659aea7..2ebfac79161fe 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -739,15 +739,17 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; status = "okay"; }; +&pcieport0 { + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l1e_0p88>; vdda-pll-supply = <&vreg_l3e_1p2>; @@ -756,15 +758,17 @@ }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { vdda-phy-supply = <&vreg_l3c_0p91>; vdda-pll-supply = <&vreg_l3e_1p2>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index a050ad18123de..2678efe088ca9 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -858,9 +858,6 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -868,6 +865,9 @@ }; &pcieport0 { + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts index 8b672939791a9..8fbf948d7a41d 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts @@ -510,13 +510,16 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcieport0 { + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l1e_0p88>; vdda-pll-supply = <&vreg_l3e_1p2>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts index 8a484489ad731..1567c376c3c03 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts @@ -584,15 +584,17 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcieport0 { + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&pm8550vs_2_l1>; vdda-pll-supply = <&pm8550vs_2_l3>; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 7a56d2625014c..e1e38850fac67 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2017,9 +2017,6 @@ power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - operating-points-v2 = <&pcie0_opp_table>; status = "disabled"; @@ -2071,6 +2068,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie0_phy>; }; }; @@ -2184,9 +2183,6 @@ power-domains = <&gcc PCIE_1_GDSC>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - operating-points-v2 = <&pcie1_opp_table>; status = "disabled"; @@ -2237,7 +2233,7 @@ }; }; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2245,6 +2241,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie1_phy>; }; }; From a45129775ebf2ffbe29c5cf5db71d0fca1bfd3f9 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:10 +0530 Subject: [PATCH 33/36] FROMLIST: arm64: dts: qcom: talos: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys from the controller to pcie_port0, and move perst-gpios/wake-gpios from the &pcie controller overrides to the &pcie_port0 node in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-34-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 8 +++++--- arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 8 +++++--- arch/arm64/boot/dts/qcom/talos.dtsi | 5 ++--- 3 files changed, 12 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index ddf94d6b39ca9..898fe47d5f5c8 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -523,15 +523,17 @@ }; &pcie { - perst-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcie_port0 { + reset-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>; +}; + &pcie_phy { vdda-phy-supply = <&vreg_l5a>; vdda-pll-supply = <&vreg_l12a>; diff --git a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi index 71095874d65e9..69a375e0c73eb 100644 --- a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi +++ b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi @@ -442,15 +442,17 @@ }; &pcie { - perst-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcie_port0 { + reset-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>; +}; + &pcie_phy { vdda-phy-supply = <&vreg_l5a>; vdda-pll-supply = <&vreg_l12a>; diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 3dd9fb230fee9..043d8f9495e1f 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -1394,9 +1394,6 @@ power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie_phy>; - phy-names = "pciephy"; - max-link-speed = <2>; operating-points-v2 = <&pcie_opp_table>; @@ -1428,6 +1425,8 @@ #size-cells = <2>; ranges; bus-range = <0x01 0xff>; + + phys = <&pcie_phy>; }; }; From 7f29363bc24abe7d72a066e973cb2a13211490dc Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:11 +0530 Subject: [PATCH 34/36] FROMLIST: arm64: dts: qcom: sm8650: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to the existing pcieport0 and pcie1_port0, allowing board-level overrides. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-35-2744251b1181@oss.qualcomm.com/ --- .../boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts | 14 ++++++++------ arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 14 ++++++++------ arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 16 ++++++++++------ arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 6 +++--- arch/arm64/boot/dts/qcom/sm8650.dtsi | 10 ++++------ 5 files changed, 33 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts index 2123312d88f6b..74a286bf76960 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts @@ -1074,9 +1074,6 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -1084,6 +1081,9 @@ }; &pcieport0 { + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; @@ -1108,15 +1108,17 @@ }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; +}; + &pcie1_port0 { /* Renesas μPD720201 PCIe USB3.0 HOST CONTROLLER */ usb-controller@0 { diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index 92b10ba13710b..779a1575e03ea 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -942,9 +942,6 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -952,6 +949,9 @@ }; &pcieport0 { + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; @@ -976,15 +976,17 @@ }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { vdda-phy-supply = <&vreg_l3e_0p9>; vdda-pll-supply = <&vreg_l3i_1p2>; diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index 8dc24db239bb5..fc17ada8cb56f 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -642,15 +642,17 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcieport0 { + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l1i_0p88>; vdda-pll-supply = <&vreg_l3i_1p2>; @@ -659,15 +661,17 @@ }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { vdda-phy-supply = <&vreg_l3e_0p9>; vdda-pll-supply = <&vreg_l3i_1p2>; diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index 70b3f0c4b6e3e..70a53b0ad46cf 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -893,9 +893,6 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -903,6 +900,9 @@ }; &pcieport0 { + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 842396cf75d95..554cbc9f759ed 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3644,9 +3644,6 @@ num-lanes = <2>; bus-range = <0 0xff>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0 0x00000000 0 0x60200000 0 0x100000>, @@ -3703,6 +3700,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie0_phy>; }; }; @@ -3824,9 +3823,6 @@ num-lanes = <2>; bus-range = <0 0xff>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - dma-coherent; #address-cells = <3>; @@ -3890,6 +3886,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie1_phy>; }; }; From e2467e85436cd20cbc67279fa6e62e217e5d5f2d Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:12 +0530 Subject: [PATCH 35/36] FROMLIST: arm64: dts: qcom: kodiak: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst/wake GPIO properties are per-root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys from the controller to pcie0_port and pcie1_port0, and move perst-gpios/wake-gpios from the &pcie0/&pcie1 controller overrides to the respective &pcie0_port/&pcie1_port0 nodes in the board files, renaming perst-gpios to reset-gpios to match the binding. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-36-2744251b1181@oss.qualcomm.com/ --- .../boot/dts/qcom/qcm6490-particle-tachyon.dts | 15 ++++++++++----- .../qcs6490-rb3gen2-industrial-mezzanine.dtso | 4 ++-- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 4 ++-- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 5 ++++- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 5 ++++- arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++++------ 6 files changed, 26 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts index ba01677f64cb3..536088f19b31f 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts @@ -549,15 +549,17 @@ }; &pcie0 { - perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>; pinctrl-names = "default"; status = "okay"; }; +&pcie0_port { + reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l10c_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; @@ -566,8 +568,6 @@ }; &pcie1 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>; pinctrl-names = "default"; @@ -576,6 +576,11 @@ status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { vdda-phy-supply = <&vreg_l10c_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso index 7a623062bb388..00a689d421f8c 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso @@ -81,8 +81,6 @@ }; &pcie0 { - perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>; pinctrl-names = "default"; @@ -107,6 +105,8 @@ }; &pcie0_port { + reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index ef4055f3b364a..31d7113bfea01 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -976,8 +976,6 @@ }; &pcie1 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>; pinctrl-names = "default"; @@ -1002,6 +1000,8 @@ }; &pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + pcie@0,0 { compatible = "pci1179,0623"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 5c5e4f1dd2217..9198377c2a8c1 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -472,10 +472,13 @@ ap_i2c_tpm: &i2c14 { pinctrl-names = "default"; pinctrl-0 = <&pcie1_clkreq_n>, <&ssd_rst_l>, <&pe_wake_odl>; - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&pp3300_ssd>; }; +&pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; +}; + &pm8350c_pwm { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index ccd39a1baeda5..9df9cc796024a 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -418,7 +418,6 @@ &pcie1 { status = "okay"; - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&nvme_3v3_regulator>; @@ -426,6 +425,10 @@ pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>; }; +&pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index d713ace388067..6c5acc9a95499 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2323,9 +2323,6 @@ power-domains = <&gcc GCC_PCIE_0_GDSC>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - pinctrl-names = "default"; pinctrl-0 = <&pcie0_clkreq_n>; dma-coherent; @@ -2337,6 +2334,8 @@ reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie0_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -2453,9 +2452,6 @@ power-domains = <&gcc GCC_PCIE_1_GDSC>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - pinctrl-names = "default"; pinctrl-0 = <&pcie1_clkreq_n>; @@ -2471,6 +2467,8 @@ reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie1_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; From 38eb3c62de5df77aed432618252ae4d13f469e2b Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:13 +0530 Subject: [PATCH 36/36] FROMLIST: arm64: dts: qcom: msm8996: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to pcie0_port0, pcie1_port0, and pcie2_port0, adding labels to these nodes to allow board-level overrides. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board files, renaming perst-gpios to reset-gpios to match the binding. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/all/20260611-wake-v2-37-2744251b1181@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 15 ++++++++++++--- .../boot/dts/qcom/msm8996-oneplus-common.dtsi | 5 ++++- .../boot/dts/qcom/msm8996-sony-xperia-tone.dtsi | 7 +++++-- .../boot/dts/qcom/msm8996-xiaomi-common.dtsi | 4 +++- arch/arm64/boot/dts/qcom/msm8996.dtsi | 11 +++++------ 5 files changed, 29 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index 5b2e88915c2fd..ec0e18b9ebe88 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -459,23 +459,32 @@ &pcie0 { status = "okay"; - perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&wlan_en>; vdda-supply = <&vreg_l28a_0p925>; }; +&pcie0_port0 { + reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; +}; + &pcie1 { status = "okay"; - perst-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>; vdda-supply = <&vreg_l28a_0p925>; }; +&pcie1_port0 { + reset-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>; +}; + &pcie2 { status = "okay"; - perst-gpios = <&tlmm 114 GPIO_ACTIVE_LOW>; vdda-supply = <&vreg_l28a_0p925>; }; +&pcie2_port0 { + reset-gpios = <&tlmm 114 GPIO_ACTIVE_LOW>; +}; + &pcie_phy { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi index 63ab564655bc8..147d877ca4fff 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi @@ -210,12 +210,15 @@ }; &pcie0 { - perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&wlan_en>; vdda-supply = <&vreg_l28a_0p925>; status = "okay"; }; +&pcie0_port0 { + reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; +}; + &pcie_phy { vdda-phy-supply = <&vreg_l28a_0p925>; vdda-pll-supply = <&vreg_l12a_1p8>; diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi index 5b42c266557ab..20b5eeef46e47 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi @@ -191,13 +191,16 @@ }; &pcie0 { - perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&wlan_en>; vdda-supply = <&pm8994_l28>; status = "okay"; }; +&pcie0_port0 { + reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; +}; + &pcie_phy { vdda-phy-supply = <&pm8994_l28>; vdda-pll-supply = <&pm8994_l12>; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 337db4db9895a..7726326426bce 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -278,8 +278,10 @@ /* Supplied by vdd_3v3, but choose wlan_en to drive enable pin high */ vddpe-3v3-supply = <&wlan_en>; vdda-supply = <&vreg_l28a_0p925>; +}; - perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; +&pcie0_port0 { + reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 33608b1d7d060..a1b162f9e5c22 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1951,7 +1951,7 @@ "bus_master", "bus_slave"; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2028,7 +2028,7 @@ "bus_master", "bus_slave"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2052,9 +2052,6 @@ reg-names = "parf", "dbi", "elbi","config"; - phys = <&pciephy_2>; - phy-names = "pciephy"; - #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>, @@ -2102,7 +2099,7 @@ "bus_master", "bus_slave"; - pcie@0 { + pcie2_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2110,6 +2107,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pciephy_2>; }; }; };