diff --git a/drivers/firmware/qcom/memory_dump_dev.c b/drivers/firmware/qcom/memory_dump_dev.c
index 23b5d057a174c..a98c157e4f66b 100644
--- a/drivers/firmware/qcom/memory_dump_dev.c
+++ b/drivers/firmware/qcom/memory_dump_dev.c
@@ -355,6 +355,37 @@ static const struct dump_item hamoa_items[] = {
 	{ ETFSWAO_REG, 0x1000, "etfswao-reg" },
 };
 
+static const struct dump_item shikra_items[] = {
+	{ C0_CONTEXT, 0x800, "c0-context" },
+	{ C100_CONTEXT, 0x800, "c100-context" },
+	{ C200_CONTEXT, 0x800, "c200-context" },
+	{ C300_CONTEXT, 0x800, "c300-context" },
+	{ C0_SCANDUMP, 0x10000, "c0-scandump" },
+	{ C100_SCANDUMP, 0x10000, "c100-scandump" },
+	{ C200_SCANDUMP, 0x10000, "c200-scandump" },
+	{ C300_SCANDUMP, 0x40000, "c300-scandump" },
+	{ L1_ICACHE0, 0x8900, "l1-icache0" },
+	{ L1_ICACHE100, 0x8900, "l1-icache100" },
+	{ L1_ICACHE200, 0x8900, "l1-icache200" },
+	{ L1_ICACHE300, 0x8900, "l1-icache300" },
+	{ L1_DCACHE0, 0x9100, "l1-dcache0" },
+	{ L1_DCACHE100, 0x9100, "l1-dcache100" },
+	{ L1_DCACHE200, 0x9100, "l1-dcache200" },
+	{ L1_DCACHE300, 0x9100, "l1-dcache300" },
+	{ L2_TLB0, 0x2100, "l2-tlb0" },
+	{ L2_TLB100, 0x2100, "l2-tlb100" },
+	{ L2_TLB200, 0x2100, "l2-tlb200" },
+	{ L2_TLB300, 0x2100, "l2-tlb300" },
+	{ RPM_SW, 0x30000, "rpm-sw" },
+	{ PMIC, 0x40000, "pmic" },
+	{ FCM, 0x8400, "fcm" },
+	{ TMC_ETF, 0x8000, "tmc-etf" },
+	{ ETR_REG, 0x1000, "etr-reg" },
+	{ ETF_REG, 0x1000, "etf-reg" },
+	{ MISC_DATA, 0x1000, "misc-data" },
+	{ ETF_LPASS, 0x8000, "etf-lpass" },
+};
+
 static const struct dump_table lemans_dump_table = {
 	.items		= lemans_items,
 	.num_of_items	= ARRAY_SIZE(lemans_items),
@@ -397,6 +428,13 @@ static const struct dump_table hamoa_dump_table = {
 	.imem_size	= 0x8,
 };
 
+static const struct dump_table shikra_dump_table = {
+	.items		= shikra_items,
+	.num_of_items	= ARRAY_SIZE(shikra_items),
+	.imem_base	= 0xc11e010,
+	.imem_size	= 0x8,
+};
+
 static int __init mem_dump_dev_init(void)
 {
 	int ret;
@@ -479,6 +517,14 @@ static int __init mem_dump_dev_init(void)
 			goto fail;
 
 		break;
+	case 756:
+	case 758:
+	case 759:
+		ret = platform_device_add_data(mem_dump_pdev,
+				&shikra_dump_table, sizeof(shikra_dump_table));
+		if (ret)
+			goto fail;
+		break;
 	default:
 		dev_err(&mem_dump_pdev->dev, "Invalid SoC ID\n");
 		ret = -EINVAL;
diff --git a/drivers/misc/qcom-dcc-dev.c b/drivers/misc/qcom-dcc-dev.c
index 6f9f1004587ae..8242f5ca0759f 100644
--- a/drivers/misc/qcom-dcc-dev.c
+++ b/drivers/misc/qcom-dcc-dev.c
@@ -11,6 +11,7 @@
 #include "qcom-dcc-lemans-config.h"
 #include "qcom-dcc-kodiak-config.h"
 #include "qcom-dcc-pakala-config.h"
+#include "qcom-dcc-shikra-config.h"
 
 #define DEV_NAME "qcom-dcc"
 
@@ -112,6 +113,13 @@ static int __init dcc_dev_init(void)
 			goto fail;
 
 		break;
+	case 756:
+	case 758:
+	case 759:
+		ret = platform_device_add_data(dcc_pdev, &shikra_pdata, sizeof(shikra_pdata));
+		if (ret)
+			goto fail;
+		break;
 	default:
 		pr_err("DCC: Invalid SoC ID\n");
 		ret = -EINVAL;
diff --git a/drivers/misc/qcom-dcc-shikra-config.h b/drivers/misc/qcom-dcc-shikra-config.h
new file mode 100644
index 0000000000000..fdf3d0c34695c
--- /dev/null
+++ b/drivers/misc/qcom-dcc-shikra-config.h
@@ -0,0 +1,677 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _QCOM_DCC_SHIKRA_CONFIG_H
+#define _QCOM_DCC_SHIKRA_CONFIG_H
+
+#include "qcom-dcc.h"
+
+static const struct dcc_register_entry shikra_dcc_entries_ll2[] = {
+	/* timer */
+	{ "R 0x17421000 2" },
+	/* clock */
+	{ "R 0x1400000 10" },
+	{ "R 0x1401000 10" },
+	{ "R 0x1402000 10" },
+	{ "R 0x1403000 10" },
+	{ "R 0x1404000 10" },
+	{ "R 0x1405000 10" },
+	{ "R 0x1406000 10" },
+	{ "R 0x1407000 10" },
+	{ "R 0x1408000 10" },
+	{ "R 0x1409000 9" },
+	{ "R 0x140a000 10" },
+	{ "R 0x140b000 10" },
+	{ "R 0x140c000 10" },
+	{ "R 0x141001c" },
+	{ "R 0x14103d0" },
+	{ "R 0x1414024" },
+	{ "R 0x1415034 2" },
+	{ "R 0x141f02c" },
+	{ "R 0x141f15c" },
+	{ "R 0x141f28c" },
+	{ "R 0x141f3bc" },
+	{ "R 0x141f4ec" },
+	{ "R 0x141f61c" },
+	{ "R 0x141f74c" },
+	{ "R 0x141f87c" },
+	{ "R 0x141f9ac" },
+	{ "R 0x141fadc" },
+	{ "R 0x141fc0c" },
+	{ "R 0x1427024" },
+	{ "R 0x1432034" },
+	{ "R 0x1434028" },
+	{ "R 0x1434154" },
+	{ "R 0x143c018" },
+	{ "R 0x1446024" },
+	{ "R 0x1446154" },
+	{ "R 0x1449018" },
+	{ "R 0x14b4014" },
+	{ "R 0x146b000 14" },
+	{ "R 0xfa80000 6" },
+	{ "R 0xfa8001c 2" },
+	{ "R 0xfa80028" },
+	{ "R 0xfa80034 2" },
+	{ "R 0xfa80080 3" },
+	{ "R 0xfa84000 6" },
+	{ "R 0xfa8401c 2" },
+	{ "R 0xfa84028" },
+	{ "R 0xfa84034 2" },
+	{ "R 0xfa84080 3" },
+	{ "R 0xfa88000 6" },
+	{ "R 0xfa8801c 2" },
+	{ "R 0xfa88028" },
+	{ "R 0xfa88034 2" },
+	{ "R 0xfa88080 3" },
+	{ "R 0x440c000" },
+	{ "R 0x440c008" },
+	{ "R 0x440c040 9" },
+	{ "R 0x440c068 2" },
+	/* global_cpr */
+	{ "R 0x1648000 2" },
+	{ "R 0x16480e0" },
+	{ "R 0x1648100" },
+	{ "R 0x1648120" },
+	{ "R 0x1648140" },
+	{ "R 0x1648200" },
+	{ "R 0x164880c 4" },
+	{ "R 0x164c000 2" },
+	{ "R 0x164c0e0" },
+	{ "R 0x164c100" },
+	{ "R 0x164c120" },
+	{ "R 0x164c140" },
+	{ "R 0x164c200" },
+	{ "R 0x164c80c 4" },
+	{ "R 0x1b44268 7" },
+	{ "R 0x1b44288 11" },
+	{ "R 0x1b442d0" },
+	/* cpr */
+	{ "R 0xfd9001c 3" },
+	{ "R 0xfd90090" },
+	{ "R 0xfd900b0 2" },
+	{ "R 0xfd900d8" },
+	{ "R 0xfd900e8" },
+	{ "R 0xfd90300" },
+	{ "R 0xfd90320" },
+	{ "R 0xfd90348 3" },
+	{ "R 0xfd90360" },
+	{ "R 0xfd90368 2" },
+	{ "R 0xfd9101c 3" },
+	{ "R 0xfd91090" },
+	{ "R 0xfd910b0 2" },
+	{ "R 0xfd910d8" },
+	{ "R 0xfd910e8" },
+	{ "R 0xfd91300" },
+	{ "R 0xfd91320" },
+	{ "R 0xfd91348 3" },
+	{ "R 0xfd91360" },
+	{ "R 0xfd91368 2" },
+	{ "R 0xfd9201c 3" },
+	{ "R 0xfd92090" },
+	{ "R 0xfd920b0 2" },
+	{ "R 0xfd920d8" },
+	{ "R 0xfd920e8" },
+	{ "R 0xfd92300" },
+	{ "R 0xfd92320" },
+	{ "R 0xfd92348 4" },
+	{ "R 0xfd92360" },
+	{ "R 0xfd92368 2" },
+	{ "R 0xfd98004" },
+	{ "R 0xfd98018 3" },
+	{ "R 0xf900c14 2" },
+	{ "R 0xfba0008" },
+	{ "R 0xfba0020 2" },
+	{ "R 0xfba0070" },
+	{ "R 0xfba0810" },
+	{ "R 0xfba3500" },
+	{ "R 0xfba3a84 2" },
+	{ "R 0xfa90004" },
+	{ "R 0xfa92004" },
+	{ "R 0xfa94004" },
+	{ "R 0xfba3a84 3" },
+	{ "R 0xfd90200 12" },
+	{ "R 0xfd91200 12" },
+	{ "R 0xfd92200 12" },
+	{ "R 0xfba3500 40" },
+	/* cpucp */
+	{ "R 0xfd80110" },
+	{ "R 0xfd9001c" },
+	{ "R 0xfd90090" },
+	{ "R 0xfd900b0" },
+	{ "R 0xfd900d8" },
+	{ "R 0xfd900e8" },
+	{ "R 0xfd90300" },
+	{ "R 0xfd90320" },
+	{ "R 0xfd90348" },
+	{ "R 0xfd9101c" },
+	{ "R 0xfd91090" },
+	{ "R 0xfd910b0" },
+	{ "R 0xfd910d8" },
+	{ "R 0xfd910e8" },
+	{ "R 0xfd91300" },
+	{ "R 0xfd91320" },
+	{ "R 0xfd91348" },
+	{ "R 0xfd9201c" },
+	{ "R 0xfd92090" },
+	{ "R 0xfd920b0" },
+	{ "R 0xfd920d8" },
+	{ "R 0xfd920e8" },
+	{ "R 0xfd92300" },
+	{ "R 0xfd92320" },
+	{ "R 0xfd92348" },
+	{ "R 0xfd98004" },
+	{ "R 0xfd98018" },
+	{ "R 0xf900c00" },
+	{ "R 0xfb00000" },
+	{ "R 0xfba0000" },
+	{ "R 0xf800000" },
+	{ "R 0xf810000" },
+	{ "R 0xf820000" },
+	{ "R 0xf830000" },
+	{ "R 0xf840000" },
+	{ "R 0xf850000" },
+	{ "R 0xf860000" },
+	{ "R 0xf870000" },
+	{ "R 0xfd91000" },
+	{ "R 0xfd92000" },
+	{ "R 0xf880000" },
+	{ "R 0xfd90000" },
+	{ "R 0xf900c18" },
+	{ "R 0xfd9134c" },
+	{ "R 0xfd9234c" },
+	{ "R 0xfd9034c" },
+	{ "R 0xfba3a84" },
+	{ "R 0xfba3a88" },
+	{ "R 0xfba3a8c" },
+	{ "R 0xfd91020" },
+	{ "R 0xfd92020" },
+	{ "R 0xfd90020" },
+	/* modem */
+	{ "R 0x6080400 3" },
+	{ "R 0x6080410 2" },
+	{ "R 0x6080060 5" },
+	{ "R 0x61f100c" },
+	{ "R 0x143314c" },
+	{ "R 0x6140400 3" },
+	{ "R 0x6082028" },
+	{ "R 0x6080304" },
+	{ "R 0xd2f010" },
+	{ "R 0x6104000 8" },
+	{ "R 0x6140208 3" },
+	{ "R 0x6140228 3" },
+	{ "R 0x6140248 3" },
+	{ "R 0x6140268 3" },
+	{ "R 0x6140288 3" },
+	{ "R 0x6140400 3" },
+	{ "R 0x6082028" },
+	{ "R 0x6080304" },
+	{ "R 0x6140200" },
+	{ "R 0x6140404" },
+	{ "R 0x608030c" },
+	/* ICB - SYSTEM_NOC */
+	{ "R 0x1880000" },
+	{ "R 0x1880004" },
+	{ "R 0x1880008" },
+	{ "R 0x1880010" },
+	{ "R 0x1880020" },
+	{ "R 0x1880024" },
+	{ "R 0x1880028" },
+	{ "R 0x188002c" },
+	{ "R 0x1880030" },
+	{ "R 0x1880034" },
+	{ "R 0x1880038" },
+	{ "R 0x188003c" },
+	{ "R 0x1880240" },
+	{ "R 0x1880248" },
+	{ "R 0x1881018" },
+	{ "R 0x1881008" },
+	{ "R 0x1881010 2" },
+	{ "R 0x1881098" },
+	{ "R 0x1881088" },
+	{ "R 0x1881090 2" },
+	{ "R 0x1881118" },
+	{ "R 0x1881108" },
+	{ "R 0x1881110 2" },
+	{ "R 0x1881198" },
+	{ "R 0x1881188" },
+	{ "R 0x1881190 2" },
+	{ "R 0x1881218" },
+	{ "R 0x1881208" },
+	{ "R 0x1881210 2" },
+	/* ICB - CONFIG_NOC */
+	{ "R 0x1900000" },
+	{ "R 0x1900004" },
+	{ "R 0x1900008" },
+	{ "R 0x1900010" },
+	{ "R 0x1900020" },
+	{ "R 0x1900024" },
+	{ "R 0x1900028" },
+	{ "R 0x190002c" },
+	{ "R 0x1900030" },
+	{ "R 0x1900034" },
+	{ "R 0x1900038" },
+	{ "R 0x190003c" },
+	{ "R 0x1900240" },
+	{ "R 0x1900244" },
+	{ "R 0x1900248" },
+	{ "R 0x190024c" },
+	{ "R 0x1901018" },
+	{ "R 0x1901008" },
+	{ "R 0x1901010 2" },
+	{ "R 0x1901118" },
+	{ "R 0x1901108" },
+	{ "R 0x1901110 2" },
+	{ "R 0x1901218" },
+	{ "R 0x1901208" },
+	{ "R 0x1901210 2" },
+	{ "R 0x1901318" },
+	{ "R 0x1901308" },
+	{ "R 0x1901310 2" },
+	/* ICB - MEMNOC */
+	{ "R 0xd00000" },
+	{ "R 0xd00004" },
+	{ "R 0xd00008" },
+	{ "R 0xd00010" },
+	{ "R 0xd00020" },
+	{ "R 0xd00024" },
+	{ "R 0xd00028" },
+	{ "R 0xd0002c" },
+	{ "R 0xd00030" },
+	{ "R 0xd00034" },
+	{ "R 0xd00038" },
+	{ "R 0xd0003c" },
+	{ "R 0xd40000" },
+	{ "R 0xd40004" },
+	{ "R 0xd40008" },
+	{ "R 0xd40010" },
+	{ "R 0xd40020" },
+	{ "R 0xd40024" },
+	{ "R 0xd40028" },
+	{ "R 0xd4002c" },
+	{ "R 0xd40030" },
+	{ "R 0xd40034" },
+	{ "R 0xd40038" },
+	{ "R 0xd4003c" },
+	{ "R 0xd00240" },
+	{ "R 0xd00248" },
+	{ "R 0xd40440" },
+	{ "R 0xd40448" },
+	{ "R 0xd41018" },
+	{ "R 0xd41008" },
+	{ "R 0xd41010 2" },
+	{ "R 0xd01018" },
+	{ "R 0xd01008" },
+	{ "R 0xd01010 2" },
+	/* ICB - DC_NOC */
+	{ "R 0xce5018" },
+	{ "R 0xce5008" },
+	{ "R 0xce5010 2" },
+	{ "R 0xce0010" },
+	{ "R 0xce0020 8" },
+	{ "R 0xce0248" },
+	/* ICB - QoS - system noc */
+	{ "R 0x18d1010" },
+	{ "R 0x18d2010" },
+	{ "R 0x18d3010" },
+	{ "R 0x18d4010" },
+	{ "R 0x18d5010" },
+	{ "R 0x18d6010" },
+	{ "R 0x18d7010" },
+	{ "R 0x18d8010" },
+	{ "R 0x18d9010" },
+	{ "R 0x18da010" },
+	{ "R 0x18db010" },
+	{ "R 0x18dc010" },
+	{ "R 0x18dd010" },
+	{ "R 0x18de010" },
+	{ "R 0x18df010" },
+	{ "R 0x18e0010" },
+	{ "R 0x18e1010" },
+	{ "R 0x18e2010" },
+	{ "R 0x18e3010" },
+	{ "R 0x18e4010" },
+	{ "R 0x18e5010" },
+	{ "R 0x18e6010" },
+	{ "R 0x18e7010" },
+	{ "R 0x18e8010" },
+	{ "R 0x18e9010" },
+	{ "R 0x18ea010" },
+	/* ICB - QoS - mem noc */
+	{ "R 0xd28010" },
+	{ "R 0xd2a010" },
+	{ "R 0xd2b010" },
+	{ "R 0xd2c010" },
+	{ "R 0xd2d010" },
+	{ "R 0xd2e010" },
+	{ "R 0xd2f010" },
+	/* ddr */
+	{ "R 0x1089180 2" },
+	{ "R 0x10804d4" },
+	{ "R 0x10804b8 2" },
+	{ "R 0x1089100" },
+	{ "R 0x1089110" },
+	{ "R 0x1089120" },
+	{ "R 0x10891a0" },
+	{ "R 0x108340c" },
+	{ "R 0x1083404" },
+	{ "R 0x1083410" },
+	{ "R 0x1083408" },
+	{ "R 0x1083400" },
+	{ "R 0x1086418" },
+	{ "R 0x1086400" },
+	{ "R 0x1086420" },
+	{ "R 0x1086410" },
+	{ "R 0x10891c0" },
+	{ "R 0x10891e0" },
+	{ "R 0x1085b14" },
+	{ "R 0x1085b10" },
+	{ "R 0x1085b0c" },
+	{ "R 0x1085b00" },
+	{ "R 0x10853b0" },
+	{ "R 0x1085b1c" },
+	{ "R 0x1085b08" },
+	{ "R 0x1085b38" },
+	{ "R 0x1085b30" },
+	{ "R 0x1085b2c" },
+	{ "R 0x1085804" },
+	{ "R 0x1085b28" },
+	{ "R 0x1085b18" },
+	{ "R 0x1085230" },
+	{ "R 0x1085210" },
+	{ "R 0xc800b0 2" },
+	{ "R 0xcb6000" },
+	{ "R 0x1286074 5" },
+	{ "R 0x1286260 5" },
+	{ "R 0xc80018" },
+	{ "R 0xc80108" },
+	{ "R 0xc840e0 2" },
+	{ "R 0xcba070 2" },
+	{ "R 0xcba054" },
+	{ "R 0xcba078 2" },
+	{ "R 0xcba058" },
+	{ "R 0xcba080" },
+	{ "R 0xcba084" },
+	{ "R 0xcba05c" },
+	{ "R 0xcba088" },
+	{ "R 0xcba08c" },
+	{ "R 0xcba060" },
+	{ "R 0xcba090 2" },
+	{ "R 0xcba064" },
+	{ "R 0xcba098 2" },
+	{ "R 0x1090018" },
+	{ "R 0x1090110 4" },
+	{ "R 0x1090004" },
+	{ "R 0x10900a0" },
+	{ "R 0x1090170" },
+	{ "R 0x1090180 4" },
+	{ "R 0x1090078" },
+	{ "R 0x1090150 4" },
+	{ "R 0x1090080" },
+	{ "R 0x1090088" },
+	{ "R 0x1090090" },
+	{ "R 0x1090070 2" },
+	{ "R 0x10900b0" },
+	{ "R 0x1090130" },
+	{ "R 0x1090140" },
+	{ "R 0x1090030 3" },
+	{ "R 0x1090044" },
+	{ "R 0x1090144" },
+	{ "R 0x1090040 3" },
+	{ "R 0x10900c8 2" },
+	{ "R 0x1090050" },
+	{ "R 0x1090128 2" },
+	{ "R 0x10900e4 5" },
+	{ "R 0x1090124" },
+	{ "R 0x1090100" },
+	{ "R 0xe90018" },
+	{ "R 0xe90110 4" },
+	{ "R 0xe90004" },
+	{ "R 0xe900a0" },
+	{ "R 0xe90170" },
+	{ "R 0xe90180 4" },
+	{ "R 0xe90078" },
+	{ "R 0xe90150" },
+	{ "R 0xe90080" },
+	{ "R 0xe90154" },
+	{ "R 0xe90088" },
+	{ "R 0xe90158" },
+	{ "R 0xe90090" },
+	{ "R 0xe9015c" },
+	{ "R 0xe90070 2" },
+	{ "R 0xe900b0" },
+	{ "R 0xe90130" },
+	{ "R 0xe90034" },
+	{ "R 0xe90140" },
+	{ "R 0xe90038" },
+	{ "R 0xe90030" },
+	{ "R 0xe90044" },
+	{ "R 0xe90144" },
+	{ "R 0xe90048" },
+	{ "R 0xe90040" },
+	{ "R 0xe900c8 2" },
+	{ "R 0xe90050" },
+	{ "R 0xe90128 2" },
+	{ "R 0xe900e4 3" },
+	{ "R 0xe900f0 2" },
+	{ "R 0xe90124" },
+	{ "R 0xe90100" },
+	{ "R 0xf90018" },
+	{ "R 0xf90110 4" },
+	{ "R 0xf90004" },
+	{ "R 0xf900a0" },
+	{ "R 0xf90170" },
+	{ "R 0xf90180 4" },
+	{ "R 0xf90078" },
+	{ "R 0xf90150 4" },
+	{ "R 0xf90080" },
+	{ "R 0xf90088" },
+	{ "R 0xf90090" },
+	{ "R 0xf90070 2" },
+	{ "R 0xf900b0" },
+	{ "R 0xf90130 2" },
+	{ "R 0xf90140" },
+	{ "R 0xf90038" },
+	{ "R 0xf90030" },
+	{ "R 0xf90044" },
+	{ "R 0xf90144" },
+	{ "R 0xf90048" },
+	{ "R 0xf90040" },
+	{ "R 0xf900c8 2" },
+	{ "R 0xf90050" },
+	{ "R 0xf90128 2" },
+	{ "R 0xf900e4 5" },
+	{ "R 0xf90124" },
+	{ "R 0xf90100" },
+	{ "R 0xcba218" },
+	{ "R 0xcba050" },
+	{ "R 0xcba210" },
+	{ "R 0xcba280" },
+	{ "R 0xcba180 4" },
+	{ "R 0xcba214" },
+	{ "R 0xcba004" },
+	{ "R 0xcba000" },
+	{ "R 0xcba014 2" },
+	{ "R 0xcba020 2" },
+	{ "R 0xcba010" },
+	{ "R 0xcba288 7" },
+	{ "R 0xcba150 2" },
+	{ "R 0xcba200" },
+	{ "R 0xcba140 2" },
+	{ "R 0xcba230 2" },
+	{ "R 0xcba0c8 2" },
+	{ "R 0xcba0b0 4" },
+	{ "R 0xcba240 2" },
+	{ "R 0xcba250 4" },
+	{ "R 0xcba100 5" },
+	{ "R 0xcba120 3" },
+	{ "R 0xcba130" },
+	{ "R 0xcba134" },
+	{ "R 0xcba270" },
+	{ "R 0xc35008" },
+	{ "R 0xc350b4" },
+	{ "R 0xc35100" },
+	{ "R 0x1059070" },
+	{ "R 0x103801c 7" },
+	{ "R 0x1023318" },
+	{ "R 0x1020488" },
+	{ "R 0x1020480" },
+	{ "R 0x1023594" },
+	{ "R 0x102358c" },
+	{ "R 0x10223a0" },
+	{ "R 0x1022398" },
+	{ "R 0x10223ac" },
+	{ "R 0x10223a4" },
+	{ "R 0x128007c" },
+	{ "R 0x128107c" },
+	{ "R 0x128207c" },
+	{ "R 0x128307c" },
+	{ "R 0x128407c" },
+	{ "R 0x128507c" },
+	{ "R 0x12800a4" },
+	{ "R 0x12810a4" },
+	{ "R 0x12820a4" },
+	{ "R 0x12830a4" },
+	{ "R 0x12840a4" },
+	{ "R 0x12850a4" },
+	{ "R 0x1280100" },
+	{ "R 0x1281100" },
+	{ "R 0x1282100" },
+	{ "R 0x1283100" },
+	{ "R 0x1284100" },
+	{ "R 0x1285100" },
+	{ "R 0x128011c" },
+	{ "R 0x128111c" },
+	{ "R 0x128211c" },
+	{ "R 0x128311c" },
+	{ "R 0x128411c" },
+	{ "R 0x128511c" },
+	{ "R 0x1280568" },
+	{ "R 0x1281568" },
+	{ "R 0x1282568" },
+	{ "R 0x1283568" },
+	{ "R 0x1284568" },
+	{ "R 0x1285568" },
+	{ "R 0x128082c" },
+	{ "R 0x128182c" },
+	{ "R 0x128282c" },
+	{ "R 0x128382c" },
+	{ "R 0x128482c" },
+	{ "R 0x128582c" },
+	{ "R 0x128007c" },
+	{ "R 0x128107c" },
+	{ "R 0x128207c" },
+	{ "R 0x128307c" },
+	{ "R 0x128407c" },
+	{ "R 0x128507c" },
+	{ "R 0x12800a4" },
+	{ "R 0x12810a4" },
+	{ "R 0x12820a4" },
+	{ "R 0x12830a4" },
+	{ "R 0x12840a4" },
+	{ "R 0x12850a4" },
+	{ "R 0xc80058 2" },
+	{ "R 0xc800c8" },
+	{ "R 0xc800d4" },
+	{ "R 0xc80114" },
+	{ "R 0xc80104 2" },
+	{ "R 0xc800b0 2" },
+	{ "R 0xc80098" },
+	{ "R 0xd00248" },
+};
+
+static const struct dcc_register_entry shikra_dcc_entries_ll3[] = {
+	/* gpu */
+	{ "R 0x599106c" },
+	{ "R 0x599100c" },
+	{ "R 0x59910a4" },
+	{ "R 0x5991054" },
+	{ "R 0x5991098 2" },
+	{ "R 0x5991078" },
+	{ "R 0x5991508" },
+	{ "R 0x599150c" },
+	{ "R 0x143600c" },
+	{ "R 0x1471000" },
+	{ "R 0x1436018" },
+	/* cdsp */
+	{ "R 0xb3b0208 3" },
+	{ "R 0xb3b0228 3" },
+	{ "R 0xb3b0248 3" },
+	{ "R 0xb3b0268 3" },
+	{ "R 0xb3b0290" },
+	{ "R 0xb3b02b0" },
+	{ "R 0xb3b0400 3" },
+	{ "R 0xb302028" },
+	{ "R 0xb300304" },
+	{ "R 0xb3b0200" },
+	{ "R 0xb3b0404" },
+	{ "R 0x608030c" },
+	/* apps_pcu */
+	{ "R 0xf800024" },
+	{ "R 0xf800040" },
+	{ "R 0xf80004c" },
+	{ "R 0xf800054" },
+	{ "R 0xf810024" },
+	{ "R 0xf810040" },
+	{ "R 0xf81004c" },
+	{ "R 0xf810054" },
+	{ "R 0xf820024" },
+	{ "R 0xf820040" },
+	{ "R 0xf82004c" },
+	{ "R 0xf820054" },
+	{ "R 0xf830024" },
+	{ "R 0xf830040" },
+	{ "R 0xf83004c" },
+	{ "R 0xf830054" },
+	{ "R 0xf880024" },
+	{ "R 0xf880040" },
+	{ "R 0xf880098" },
+	{ "R 0xfa80000 2" },
+	{ "R 0xfa84000 2" },
+	{ "R 0xfa88000 2" },
+	{ "R 0xf880200" },
+	{ "R 0xf8801b4 3" },
+	{ "R 0xf880044 3" },
+	{ "R 0xf880054" },
+	{ "R 0xf88006c" },
+	{ "R 0xf880070 4" },
+	{ "R 0xfd90348 2" },
+	{ "R 0xfd91348 2" },
+	{ "R 0xfd92348 2" },
+	{ "R 0xfd800fc" },
+	{ "R 0xfd800ec" },
+	{ "R 0xfd8010c" },
+	{ "R 0xfd91060 8" },
+	{ "R 0xfd92064 8" },
+};
+
+static const struct dcc_link_config shikra_link_configs[] = {
+	{
+		.link_list	= 2,
+		.entries	= shikra_dcc_entries_ll2,
+		.num_entries	= ARRAY_SIZE(shikra_dcc_entries_ll2),
+	},
+	{
+		.link_list	= 3,
+		.entries	= shikra_dcc_entries_ll3,
+		.num_entries	= ARRAY_SIZE(shikra_dcc_entries_ll3),
+	},
+};
+
+static const struct dcc_config shikra_config = {
+	.lists		= shikra_link_configs,
+	.num_lists	= ARRAY_SIZE(shikra_link_configs),
+};
+
+static const struct dcc_pdata shikra_pdata = {
+	.base		= 0x080ff000,
+	.size		= 0x00001000,
+	.ram_base	= 0x08086000,
+	.ram_size	= 0x00002000,
+	.dcc_offset	= 0x6000,
+	.map_ver	= 0x3,
+	.config		= &shikra_config,
+};
+
+#endif /* _QCOM_DCC_SHIKRA_CONFIG_H */