Add missing Neon intrinsics by MartinWehking · Pull Request #440 · ARM-software/acle

MartinWehking · 2026-07-07T10:05:28Z

These intrinsics are present in LLVM and GCC, but not documented on the ACLE.
Add them to close the gap.

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These intrinsics are present in LLVM and GCC, but not documented on the ACLE. Add them to close the gap.

CarolineConcatto · 2026-07-09T07:57:05Z

 | <code>poly8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p8" target="_blank">vmovq_n_p8</a>(poly8_t value)</code>                                                                                         | `value -> rn`                        | `DUP Vd.16B,rn`         | `Vd.16B -> result` | `v7/A32/A64`              |
 | <code>poly16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p16" target="_blank">vmov_n_p16</a>(poly16_t value)</code>                                                                                        | `value -> rn`                        | `DUP Vd.4H,rn`          | `Vd.4H -> result`  | `v7/A32/A64`              |
 | <code>poly16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p16" target="_blank">vmovq_n_p16</a>(poly16_t value)</code>                                                                                      | `value -> rn`                        | `DUP Vd.8H,rn`          | `Vd.8H -> result`  | `v7/A32/A64`              |
+| <code>poly64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p64" target="_blank">vmov_n_p64</a>(poly64_t value)</code>                                                                                        | `value -> rn`                        | `INS Dd.D[0],xn`        | `Vd.1D -> result`  | `A32/A64`                 |


Is this correct ' INS Dd.D[0],xn`, it is different from the others vmovq with poly types.

For both GCC and LLVM, the compiler is emitting a fmov in assembly.
Fr other intrinsics fmov is an INS rather than a DUP:
https://godbolt.org/z/WojWWKrss

vmovq on the other hand emits a "real" DUP in assembly.

Compare vdup_n_p64, which is also emitting an INS only.

This doesn't make sense as is:

INS here implies a partial (merging) write to the destination register but this intrinsic does not specify a destination to merge into (it wouldn't make sense to do so either).

INS with a Dd (not Vd) destination doesn't exist in AArch64 at least.

So I think this should be FMOV since that is the closest correct interpretation (and that's what compilers currently emit anyway for the GPR->VPR mov).

INS with a Dd (not Vd) destination doesn't exist in AArch64 at least.

vdup_n_p64 is also wrong then: INS Dd.D[0],xn, so this needs changed.

There is no intrinsic that lists FMOV as AArch64 Instruction. I don't mind changing it, though

Martin I agree with George and I am in favour to update this to what the compilers are lowering to, which is FMOV

ah, sorry yes, I updated this in the latest commit:

| <code>poly64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p64" target="_blank">vmov_n_p64</a>(poly64_t value)</code> | `value -> rn` | `FMOV Dd,rn` | `Vd.1D -> result` | `A32/A64` |

The other INS to FMOV changes are here:
#445

CarolineConcatto · 2026-07-09T07:58:01Z

 | <code>poly8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p8" target="_blank">vmovq_n_p8</a>(poly8_t value)</code>                                                                                         | `value -> rn`                        | `DUP Vd.16B,rn`         | `Vd.16B -> result` | `v7/A32/A64`              |
 | <code>poly16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p16" target="_blank">vmov_n_p16</a>(poly16_t value)</code>                                                                                        | `value -> rn`                        | `DUP Vd.4H,rn`          | `Vd.4H -> result`  | `v7/A32/A64`              |
 | <code>poly16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p16" target="_blank">vmovq_n_p16</a>(poly16_t value)</code>                                                                                      | `value -> rn`                        | `DUP Vd.8H,rn`          | `Vd.8H -> result`  | `v7/A32/A64`              |
+| <code>poly64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p64" target="_blank">vmov_n_p64</a>(poly64_t value)</code>                                                                                        | `value -> rn`                        | `INS Dd.D[0],xn`        | `Vd.1D -> result`  | `A32/A64`                 |


Should we change this to also report v7?

I wish I could give a strong reason why it should be/ shouldn't be v7, but all I can do is base it on patterns:

vmovq_n_p64 also uses A32/A64 only.
Most other _p64intrinsics such as vcombine_p64 are also just A32/A64.

These intrinsics were also present in LLVM/gcc. Inside the LLVM backend they are currently guarded only by A64 flags, but should be A32 probably as well.

Do you think it should be v7 or do you perhaps know how I could definitely say it is/isn't v7?

The primary use case for 64-bit polynomial types would be to use the PMULL instruction, but that is limited to A32/A64 as well, so I think the restriction makes sense here (but it's not really a problem to have it in v7 either so no strong preference).

Same comment about INS not making sense here.

Ok, so there is no reason for this to be available in v7. Ok, A32/A64 is ok

CarolineConcatto · 2026-07-09T08:03:04Z

 poly8x16_t vmovq_n_p8(poly8_t value)	value -> rn	DUP Vd.16B,rn	Vd.16B -> result	v7/A32/A64
 poly16x4_t vmov_n_p16(poly16_t value)	value -> rn	DUP Vd.4H,rn	Vd.4H -> result	v7/A32/A64
 poly16x8_t vmovq_n_p16(poly16_t value)	value -> rn	DUP Vd.8H,rn	Vd.8H -> result	v7/A32/A64
+poly64x1_t vmov_n_p64(poly64_t value)	value -> rn	INS Dd.D[0],xn	Vd.1D -> result	A32/A64


This looks strange too.

This is the original input file. The md gets generated from the csv, so I set the value here. The strangeness was carried into the md file, so to speak

Change the changes documentation.

MartinWehking added 2 commits July 7, 2026 08:53

Add missing Neon intrinsics

30c06f2

These intrinsics are present in LLVM and GCC, but not documented on the ACLE. Add them to close the gap.

Describe the changes

85fc3f0

MartinWehking added the bugfix Bug fixes label Jul 7, 2026

CarolineConcatto reviewed Jul 9, 2026

View reviewed changes

MartinWehking added 2 commits July 15, 2026 10:14

Address comments

494dcf5

Change the changes documentation.

Make the assembly operand generic and use FMOV

53d535f

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MartinWehking commented Jul 7, 2026

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MartinWehking Jul 15, 2026 •

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