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Add Python bindings for SYCL IPC memory via dpctl#2331

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zxue2:enable_ipc_mem
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Add Python bindings for SYCL IPC memory via dpctl#2331
zxue2 wants to merge 5 commits into
IntelPython:masterfrom
zxue2:enable_ipc_mem

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@zxue2

@zxue2 zxue2 commented Jun 30, 2026

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Add inter-process communication (IPC) support for SYCL USM memory, enabling zero-copy GPU memory sharing across processes. It wraps sycl::ext::oneapi::experimental::ipc::memory (get/open/close/put).

C API (libsyclinterface):

  • dpctl_sycl_ipc_memory_interface.h: declares DPCTLIPCMem_GetHandle, DPCTLIPCMem_OpenHandle, DPCTLIPCMem_CloseHandle, DPCTLIPCMem_FreeHandleData
  • dpctl_sycl_ipc_memory_interface.cpp: implements the C API by calling the SYCL experimental ipc::memory functions; auto-discovered by CMake.

Cython declarations:

  • _backend.pxd: extern block for the 4 new C functions

Python subpackage (dpctl.ipc):

  • IPCMemoryHandle: Cython extension class wrapping IPC memory export/import init(usm_memory): calls get() + put(), stores handle as bytes to_bytes(): serializable payload for cross-process transport open(handle_bytes, device, nbytes): returns MemoryUSMDevice close_mapping(usm_memory): explicitly closes an IPC mapping

Test In Docker (oneAPI 2026.0 installed):

python -c "
import dpctl
from dpctl.memory import MemoryUSMDevice
from dpctl.ipc import IPCMemoryHandle
d = dpctl.SyclDevice('level_zero:gpu')
q = dpctl.SyclQueue(d)
mem = MemoryUSMDevice(4096, queue=q)
h = IPCMemoryHandle(mem)
raw = h.to_bytes()
print(f'IPC handle: {len(raw)} bytes')
mem2 = IPCMemoryHandle.open(raw, d, nbytes=4096)
print(f'Opened: {mem2.nbytes} bytes on {mem2.sycl_device.name}')
IPCMemoryHandle.close_mapping(mem2)
print('close OK')
"

IPC handle: 120 bytes
Opened: 4096 bytes on Intel(R) Arc(TM) Pro B60 Graphics
close OK

Add inter-process communication (IPC) support for SYCL USM memory, enabling
zero-copy GPU memory sharing across processes. It wraps
sycl::ext::oneapi::experimental::ipc::memory (get/open/close/put).

C API (libsyclinterface):
  - dpctl_sycl_ipc_memory_interface.h: declares DPCTLIPCMem_GetHandle,
    DPCTLIPCMem_OpenHandle, DPCTLIPCMem_CloseHandle, DPCTLIPCMem_FreeHandleData
  - dpctl_sycl_ipc_memory_interface.cpp: implements the C API by calling the
    SYCL experimental ipc::memory functions; auto-discovered by CMake.

Cython declarations:
  - _backend.pxd: extern block for the 4 new C functions

Python subpackage (dpctl.ipc):
  - IPCMemoryHandle: Cython extension class wrapping IPC memory export/import
    __init__(usm_memory): calls get() + put(), stores handle as bytes
    to_bytes(): serializable payload for cross-process transport
    open(handle_bytes, device, nbytes): returns MemoryUSMDevice
    close_mapping(usm_memory): explicitly closes an IPC mapping

Signed-off-by: Zhan Xue <zhan.xue@intel.com>
Comment thread dpctl/ipc/_ipc_memory.pyx Outdated
Comment thread dpctl/ipc/_ipc_memory.pyx Outdated
Comment thread dpctl/ipc/_ipc_memory.pyx Outdated
Comment thread dpctl/ipc/_ipc_memory.pyx Outdated
Comment thread dpctl/ipc/_ipc_memory.pxd Outdated
@zxue2 zxue2 force-pushed the enable_ipc_mem branch from 352d2f8 to 3dea379 Compare July 1, 2026 13:12
add has_aspect_ext_oneapi_ipc_memory checks in __init__ and open()

Signed-off-by: Zhan Xue <zhan.xue@intel.com>
@zxue2 zxue2 force-pushed the enable_ipc_mem branch from 83bb9b4 to b2c490f Compare July 2, 2026 13:22
@coveralls

coveralls commented Jul 2, 2026

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Coverage Status

coverage: 75.504% (-0.2%) from 75.677% — zxue2:enable_ipc_mem into IntelPython:master

@zxue2 zxue2 force-pushed the enable_ipc_mem branch 6 times, most recently from a626c94 to 7f907d0 Compare July 3, 2026 07:32
Signed-off-by: Zhan Xue <zhan.xue@intel.com>
Comment thread dpctl/memory/_memory.pyx

Parameters
----------
usm_memory : MemoryUSMDevice

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Is it better to use the new MemoryIPCDevice based on MemoryUSMDevice?

One more thing, I am fine with current implementation which can satisfy current demand. But restricting MemoryIPCDevice to base MemoryUSMDevice may lack extension for zeMemGetIpcHandleWithProperties that is with device or host memory allocation in future. May have a separate jira there for improvement in future.

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I figured we can extend to add additional classes later for host/shared allocations, so yes

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3 participants