Fix example board clock config. Zeroize on error returns.

[AlexLanzano]

• Fix the PLL configuration on the stm32wba example board config to properly output at 100MHz
• Make sure to zeroize any key/iv data on any failure in the crypto drivers

[Copilot]

Pull request overview

This PR corrects the STM32WBA55 Nucleo example board’s PLL1 settings to reliably produce a 100 MHz SYSCLK, and improves crypto-driver error handling by zeroizing key/IV material in more failure paths.

Changes:

• Fix PLL1 “N” configuration and document the RM0493 “value-1 encoded” divider/multiplier fields to achieve 100 MHz SYSCLK.
• Zeroize AES/CRYP peripheral key+IV registers on additional error exits (timeouts and invalid finalize parameters) in STM32WB and STM32N6 crypto drivers.

Reviewed changes

Copilot reviewed 3 out of 3 changed files in this pull request and generated 1 comment.

File	Description
src/crypto/stm32wb_aes.c	Adds ZeroKeyIv() calls on more AES error paths and cleanup/invalid-finalize returns.
src/crypto/stm32n6_cryp.c	Adds ZeroKeyIv() calls when finalize() rejects invalid tag parameters.
boards/stm32wba55cg_nucleo/board.c	Adjusts PLL1 N field and improves clocking comment to match encoded register semantics for 100 MHz SYSCLK.

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[aidangarske]

Looks good